English
DAC panel spotlights rise of IP subsystems
Dylan McGrath, EETimes
6/7/2012 1:41 AM EDT
SAN FRANCISCO—Intellectual property (IP) reuse in SoC design is increasing, creating challenges in compatibility and complexity, according to executives on a Design Automation Conference (DAC) panel. To minimize this complexity, panelists said, the semiconductor industry will increasingly turn to IP subsystems—larger chunks of IP that have been stitched together from many smaller blocks and pre-verified to ensure performance.
Naveed Sherwani, president and CEO of chip design and manufacturing services provider Open-Silicon Inc., said he was happy to see that IP reuse was finally occurring on a large scale, but said the trend is creating challenges.
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