Creonic Announces DVB-RCS2 Turbo Decoder IP Core
Kaiserslautern, Germany, Aug. 14 2012 - Creonic today announced the availability of the world's first high-efficiency turbo decoder IP core for DVB-RCS2 for the fourth quarter of 2012. After DVB-RCS, DVB-RCS2 is the second generation DVB standard for interactive satellite systems. The new standard delivers a drastically increased spectral efficiency and higher throughputs compared to its predecessor, hence clearly reducing costs of satellite modem operators.
These improvements are achieved by employment of a new 16-state double-binary turbo code that significantly outperforms its dated 8-state counterpart of DVB-RCS. DVB-RCS2 is the first standard to adopt these highest performance turbo codes, fulfilling the continuous demand for increased spectral efficiency. The outstanding error correction performance of the DVB-RCS2 turbo decoder makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.
The Creonic DVB-RCS2 turbo decoder IP core will be available for ASIC and FPGA technology and can be tailored to different throughput requirements. It furthermore offers a great block length and code rate flexibility beyond the requirements of DVB-RCS2. The IP core embodies the considerable experience of the Creonic experts in turbo decoder design as well as the latest scientific findings from academic studies. It therefore achieves highest clock frequencies and an outstanding area efficiency.
About Creonic
Creonic offers ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. The product portfolio covers standards like DVB-S2, DVB-C2, WiFi, UWB, and GMR. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information, please visit www.creonic.com.
Learn more about the DVB-RCS2 turbo decoder IP core.
|
Creonic Hot IP
Related News
- DVB-RCS2 Turbo Decoder and Encoder IP Core Available For Integration From Global IP Core
- Creonic Introduces NCR Processor IP Core for DVB-S2X/DVB-RCS2 Satellite Communication
- Creonic Releases DVB-RCS2 Multi-carrier Satellite Receiver IP Core
- DVB-RCS2 Satellite Modulator IP Core from Creonic Now Available
- Creonic Releases 4G 1 Gbit/s Turbo Decoder IP Core for LTE and LTE Advanced
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |