Arasan Chip Systems Announces the Industry Fastest SD3.0 Compliant Hardware Validation Platform
Arasan Achieved more than 90MB/s sustained read and more than 70MB/s sustained write benchmark
San Jose, California – Aug. 21, 2012 - Arasan Chip Systems, Inc. (“Arasan”), a leading provider of Total IP Solutions for mobile applications announced today the availability of the industry fastest SD 3.0 compliant hardware validation platform for engineering and product development of SD 3.0 devices with UHS-I interface. Arasan has demonstrated its SD 3.0 Hardware Validation Platform (HVP) running at more than 90MB/s sustained read and more than 70MB/s sustained write using a Linux storage device benchmark.
To meet the ever increasing data transfer rate in removable memory card applications the SD 3.0 specification calls out the maximum performance of 104MB/s running at SDR104 mode. In real applications, due to the protocol overhead and different SD 3.0 device controller designs, the actual measured performance can vary dramatically from system to system. Arasan has optimized it Linux based SD 3.0 Host HVP and tested its performance by running the Linux storage device benchmark against a SD 3.0 card from one of the leading SD card manufacturers, capable of 95MB/s read performance.
Arasan’s Hardware Validation Platforms enables early validation of the SD3 .0 specification by emulating the SD3.0 Host at the interface protocol level. Beyond this, it facilitates early application development for reference board designs and production testing, before the SD 3.0 memory cards are available in silicon. Further in the product cycle, it acts as a reference platform to help root-cause any incompatibilities between the device under development and the silicon device it is communicating with. Often, a developer of cutting edge silicon products with new standard interface protocols has no means of validating one’s design with complementary devices which themselves may be under development. When such complementary devices do become available, a full speed reference platform that faithfully adheres to the protocol and provides the accompanying software stacks is necessary to aid the bring-up of a device trying to communicate with another for the first time, followed by rapid deployment of reference boards to OEM’s and production testing of the OEM’s end products.
Arasan’s Hardware Validation Platforms (HVPs) are a key element in Arasan’s SD Total IP Solutions. Arasan, a member of the SD Association since 2001, is the leading supplier of SD 3.0 and SD 4.0 controller and PHY IP. Its Total IP Solution also includes software stacks and drivers as well as HVPs for both SD 3.0 and SD 4.0.
Availability
Arasan’s SD 3.0 Host Validation Platform is available immediately for shipment, including Linux OS based hardware with SD3.0 Host Controller FPGA board, Linux software stack in binary, and all of the customer required support files and documentation.
About Arasan
Arasan Chip Systems is a leading provider of Total IP Solutions for mobile storage and connectivity applications. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for MIPI, USB, UFS, SD, SDIO, MMC/eMMC, UFS, and many other popular standards. Arasan’s Total IP products serve system architects and chip design teams in mobile, gaming and desktop computing systems that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.
Unlike many other IP providers, Arasan’s Total IP Solution encompasses all aspects of IP development and integration, including analog and digital cores, hardware development kits, protocol analyzers, validation IP and software stacks and drivers and optional architecture consulting and customization services. Based in San Jose, CA, USA, Arasan Chip Systems has a 16 year track record of IP and IP standards development leadership.
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