Cadence supports acellera standard

Lauds Choice of Sugar 2.0 as Standard Property Specification Language

San Jose, Calif., April 26, 2002 - Cadence Design Systems, Inc. (NYSE: CDN), the world's leading supplier of electronic design products and services, announced its support for the standard property specification language defined by Accellera to enable assertion-based simulation and formal verification. The Accellera Formal Verification Technical Committee selected IBM's Sugar 2.0 language as the basis for the industry-standard language.

Cadence® supports the Accellera committee's commitment to improve design productivity through an electronic design methodology based on worldwide standards and open interfaces. Several other electronics companies and electronic design automation (EDA) companies have also expressed support for the Accellera standard including: Verplex, TransEDA, Real Intent, 0-In Design Automation, and IBM.

"Sugar 2.0 is a powerful and easy-to-understand verification language that exceeds the requirements upon which the Accellera committee based its selection," said Rahul Razdan, corporate vice president and general manager of Systems and Functional Verification at Cadence. "Its straightforward definition, together with the Sugar design team's clear documentation and open, supportive attitude toward potential implementers of the language, will help enable us to deliver support for the Accellera standard in the future."

As an industry standard, the Sugar 2.0 language will help to improve design technology interoperability and enhance the simulation and functional verification processes. Sugar 2.0 enables designers to capture specifications, requirements, and assumptions as assertions about the hardware description language (HDL) description of a digital electronic design. These assertions can be verified through simulation or formal verification. The use of assertions can greatly accelerate detection and elimination of errors during design verification.

"Although formal verification has been a rapidly growing market, the availability of a standard property specification language will hasten its expansion even further into areas well beyond equivalence checking," said Dino Caporossi, vice president of corporate marketing for Verplex, Inc. "The upcoming Accellera standard, based on Sugar 2.0, will accelerate adoption of formal design validation by enabling interoperability between simulation and formal verification flows."

"The selection of the Accellera standard property language represents a unique opportunity for the EDA community to enable a new generation of verification tools, libraries and methodologies united around a single language," said Tom Borgstrom, vice president of marketing for TransEDA, a member of the Accellera Formal Verification Technical Committee. "TransEDA is committed to supporting the Accellera standard language to help the industry realize this potential."

"We are firmly behind the Accellera effort for industry-standard assertion-based language, and have demonstrated our commitment by contributing our IP to accelerate assertion standardization," said Dr. Prakash Narain, Real Intent's President and CEO. "This standardization effort will deliver enormous benefits as it elicits broadest support from tool vendors, both established and emerging, and it is applicable across different technologies such as formal and simulation providing choices to the widest customer base."

"Rapid finalization and adoption of the Accellera Formal Property Language standard is key to EDA tool interoperability and widespread adoption of assertion based verification." said Tom Anderson, VP applications at 0-In Design Automation. "The new Accellera Formal Property Language has the right balance of expressiveness for formal verification tools and intuitiveness for users. 0-In is committed to supporting the Accellera standard and will soon have a version of it's CheckerWare Library and Monitors which incorporate it, enabling interoperability with any tool that supports the standard."

"We are quite pleased to have Sugar 2.0 selected as the basis for the Accellera standard," said Dr. Yaron Wolfsthal, manager of Formal Methods at the IBM Research Laboratory in Haifa, where Sugar has been developed since 1995. "Sugar has been a very effective tool for design verification within IBM, and as the Accellera standard it will now benefit the rest of the industry. We are looking forward to the adoption of Sugar 2.0 as an EDA standard by Accellera and to rapid deployment of tools supporting Sugar by EDA vendors such as Cadence."

"The selection of Sugar 2.0 as the basis for the Accellera standard property specification language is a major milestone," said Harry Foster, chairman of the Accellera Formal Verification Technical Committee. "The next step is to turn the already quite thorough Sugar 2.0 specification into a Language Reference Manual, which will then be submitted to the Accellera Board for approval. We expect to accomplish that within the next few months."

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services are available at www.cadence.com.

For more information, please contact:

Valerie Smith
Cadence Design Systems, Inc.
408-428-5795
vsmith@cadence.com

Matt McGinnis
Armstrong Kendall Inc.
503-672-4689
matt@akipr.com