Chip design’s recycle cycle: Interview with Aart de Geus, chairman and co chief executive, Synopsys
Chris Edwards, New Electronics
September 11, 2012
Some 15 years ago, Synopsys bet on the idea that third party intellectual property (IP) would an important element of the integrated circuit business. Interviewed towards the end of the 1990s, Synopsys' cofounder Aart de Geus – now its co ceo – talked about the problems that chip designers faced as the gap between what Moore's Law could deliver and the number of transistors in a circuit they could realistically deploy per day grew larger. In that interview, de Geus said: "I am totally convinced that reuse is necessary to the advancement of silicon."
E-mail This Article | Printer-Friendly Page |
Related News
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X