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Altera readies cores, tools for upcoming Stratix
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Altera readies cores, tools for upcoming Stratix
By Anthony Cataldo, EE Times
April 29, 2002 (2:16 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020429S0046
SAN MATEO, Calif. — Though months away from delivering its next-generation FPGA architecture, Altera Corp. has been preparing cores and software tools so that customers can start their designs as soon as the architecture hits the streets.
The company on Monday (April 29) announced version 2.1 of its Nios soft-core embedded processor. The processor is targeted for use in Altera's Stratix devices, slated to debut in the next couple of months.
Largely because of the new routing structure used in Stratix, the 32-bit Nios' clock speed will rise from 80 to 125 MHz. Stratix's multitrack uses three route lengths, with varying drive strengths, buffers and spacing, and is designed for connecting IP cores in the FPGA fabric.
More RAM will be made available for each of the logic elements in Stratix than is made available in Altera's existing Apex FPGAs. The megaRAM blocks run at up to 300 MHz, and the largest Stratix device will cont ain 10 Mbits of memory.
Nios 2.1 will ship to all customers with valid subscriptions and will cost $495 for new subscriptions. Altera expects to start selling the first Stratix device, called the 1S25, in June.
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