MIPI Alliance M-PHY Physical Layer Gains Dominant Position for Mobile Device Applications
Delivering The Highest Performance, Most Power Efficient Data Transport Interface Technology
Piscataway, NJ, September 19, 2012 – MIPI Alliance today announced its M-PHY low power, scalable physical layer specification is now the preferred data transport interface technology for mobile applications, based on previously announced relationships with JEDEC UFS, PCI-SIG®, USB-IF– and its member adoption rate. M-PHY supports storage (Universal Flash Storage or UFS), high speed chip to chip communications such as USB-IF’s SuperSpeed Interchip (SSIC) and MIPI’s Low Latency Interface (LLI), as well as MIPI’s next generation camera / display protocols. The recently announced PCI Express support will allow for linking to high-performance peripherals such as 60-GHz wireless networking controllers and solid-state drives. For more information, visit www.mipi.org
“Out of the three billion MIPI powered ICs to be shipped this year, we foresee that only 100 to 150 million ICs will integrate M-PHY support,” said Dr. Eric Esteve from IPNEST. “However, we expect the shipment of MIPI M-PHY powered ICs to grow very rapidly to reach two billion ICs in 2015, with M-PHY adoption in the high end segment of smartphone, ultrabook and media tablets.”
"We see an obvious trend towards more data-intensive applications in mobile devices, with faster communications channels, higher resolution images, higher video frame rates and larger displays," said Brian O'Rourke, Senior Principal Analyst with IHS. "MIPI's D-PHY interface is currently the dominant technology in mobile devices and we anticipate that its M-PHY interface will follow suit."
Optimized for mobile applications, M-PHY delivers an exceptionally wide data rate range spanning 10kbps to near 6Gbps. Bandwidth can be scaled based on the application needs, by selecting from several available transmission rates or by scaling up to multiple transmission lanes. Multiple transmission modes plus a low energy per bit threshold rate equals significant power efficiency. In addition, M-PHY is optical friendly, delivering an optional low-complexity electro-optical signal conversion. The EMI/RF friendly M-PHY operates well in multi-radio environments where interference thresholds are extremely low.
“M-PHY has truly become the de-facto standard for mobile device applications requiring a low-power, scalable solution,” said Joel Huloux, Chairman of the Board of MIPI Alliance. “We are pleased to join with our partners at JEDEC, USB IF, and PCI-SIG, and MIPI member companies, to advance solutions that push the envelope in interface technology.”
"Our relationship with MIPI Alliance, and the M-PHY technology, has proven very fruitful over the years," said Mian Quddus, Chairman of the JEDEC Board of Directors and the JC-64 Committee for Embedded Memory Storage and Removable Memory Cards Flash Memory Modules. "Our UFS Interconnect Layer leverages M-PHY to achieve the highest performance and most power efficient data transport for both embedded and removable flash memory-based storage in mobile devices. The UFS standard represents an evolutionary progression of JEDEC standards, and we are able to meet our goals of high performance and low power consumption with the help of M-PHY."
"The PCI-SIG® is pleased to collaborate with the MIPI Alliance to extend the ubiquitous PCI Express® architecture to operate with the mobile-optimized M-PHY specification," said Al Yanes, chairman and president, PCI-SIG. "This collaboration will enable us to couple the benefits of the PCIe® load-store I/O architecture with the low power M-PHY physical layer to deliver a seamless, power-efficient mobile user experience."
"The collaboration between MIPI Alliance and the USB Promoters Group has produced the SuperSpeed Inter-Chip (SSIC) interface, bringing USB inside the mobile device," said Brad Saunders, Chairman/Secretary of the USB 3.0 Promoters Group. "By enabling SuperSpeed USB to operate over the M-PHY physical layer, a broad range of USB-enabled functions can now migrate into the non-PC market. And MIPI's low-power physical layer technology makes it possible for the PC ecosystem to benefit from the SSIC chip-to-chip interface.”
About MIPI Alliance
MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem and are committed to defining and promoting interface specifications for mobile devices. MIPI Specifications establish standards for hardware and software interfaces which drive new technology and enable faster deployment of new features and services.
|
Related News
- MIPI Alliance Launches New M-PHY and UniPro Specifications for Mobile Device Applications
- M31 Technology Develops Complete MIPI PHY Solution Targeting Mobile Device Market
- PCI-SIG and MIPI Alliance Collaborate to Extend PCI Express Technology to Mobile Devices
- Synopsys Introduces Industry's First 28-nm Multi-Gear MIPI Alliance M-PHY IP Supporting Six Standards for Mobile Applications
- MIPI UFS 3.1, M-PHY 4.1, Unipro 1.8, ONFi 4.1 and many more IP Cores are available for immediate licensing for your advanced UFS Device Applications as a complete bundled solution
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |