Dolphin Integration measures 15% area reduction on 65 nm logic circuit with its 6-Track standard cell library
Grenoble, France – September, 21 2012 -- Dolphin Integration today announced the availability of benchmark results on real conditions at TSMC 65 nm LP process, comparing its SESAME uHD-BTF DV standard cell with a 7-Track library:
Highlights:
- SESAME uHD-BTF DV standard cell is 9% to 15% denser after P&R compared to standard 7-Track Library
- Leakage power is reduced 6 times in worst case conditions (SS; 1.08 V; -40°C)
- Low Voltage Capability for additional power savings when operating down to 0.9 V +/-10%
SESAME uHD-BTF DV benefits from replacing classical D flip-flops with pulsed latches acting as “spinner cells”. The main advantage of the spinner cell is a significant improvement in terms of density, 30% compared with D flip-flops!
More information on the key benefits of SESAME uHD-BTF DV standard cell library is available directly on the Presentation sheet
To request an access to the evaluation kit of SESAME uHD-BTF DV standard cell, contact sesame@dolphin-integration.com
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, such as mixed signal high-resolution converters for audio and measurement applications, Libraries of memories and standard cells, Power management networks, Microcontrollers. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own missing EDA solutions enabling Support Engineering with Application Hardware Modeling as well as early Power and Noise assessment, plus engineering assistance for Risk Control
|
Dolphin Design Hot IP
Related News
- Dolphin Integration announce availability of their 6-Track Standard Cell Library SESAME HD for the 65 nm LP process
- Dolphin Integration introduces a new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%
- Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm
- 90% Reduction in power consumption for RFID chips with Dolphin Integration's SESAME eLC standard cell library
- Save up to 20 % of silicon area with Dolphin Integration's standard cell library SESAME uHD
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |