Cisco chip exec sees steady ASIC investments
Rick Merritt, EETimes
9/27/2012 9:28 AM EDT
SAN JOSE, Calif. – Competitors of Cisco Systems have been talking smack lately, claiming the router giant is increasingly turning to off-the-shelf chips instead of building its own ASICs. Not so, says one of the router and switch giants top silicon honchos in an exclusive interview with EE Times.
“Our investments [in ASICs] have been and continue to be large,” said Dan Lenoski who manages a team of about 125 of Cisco’s 750 chip designers. “That investment has been steady and increased since in 2000 because communications interfaces are getting faster,” Lenoski explained.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- eASIC Announces Next Phase of Structured ASIC Business Strategy - Stepping up from a Structured ASIC IP provider to a fabless semiconductor
- TTTech divests strategic stake in landmark transaction to NXP to fuel future growth with technology investments in core business
- PIMIC Unveils Business Strategy, and Silicon Technology to Revolutionize AI at the Edge
- NanoXplore acquires Dolphin Design's ASIC business and strengthens its strategic position in aerospace
- Kalray, Arteris, Secure-IC, and Thales, Win the Call for Projects Related to the AI Acceleration Strategy of the "France Relance 2030 - Future Investments" Plan
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset