7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Research Project for Energy-efficient Risk Management has Started
Kaiserslautern, Oct. 1 2012 - The ESR research project (Energy-efficient simulation acceleration for risk measurement and management) has started with Creonic GmbH as project coordinator.
The precise and significant simulation of risk scenarios is essential for rating current and future portfolios and investments in the financial and insurance sectors. Even large CPU or GPU clusters can have a workload of many hours for such tasks resulting in huge energy consumption for these simulations.
The ESR project is an interdisciplinary cooperation between partners from the sectors of asset management, financial mathematics, and hardware design. The main objective is to make current reconfigurable hardware (field programmable gate arrays, FPGAs) easily applicable for users in finance and insurance markets. In this way a reduction of energy consumption of up to 90% is achievable compared to that of CPU or GPU implementations.
The technical challenge is to keep the high flexibility that is always required because of fast changing product descriptions, models and algorithms while using efficient and therefore dedicated accelerators. During the project the consortium develops a demonstrator for the acceleration of selected algorithms that are relevant for industry. This demonstrator will form the foundation for a commercial platform.
The project consortium consists of:
- Assenagon GmbH, Munich: Asset Management
- Creonic GmbH, Kaiserslautern: Hardware design for FPGAs
- cronologic GmbH & Co KG, Frankfurt: FPGA boards and integration
- Fraunhofer-Institut für Techno- und Wirtschaftsmathematik (ITWM), Kaiserslautern
- Karlsruhe Institute of Technology (KIT): Information processing technologies
- University of Kaiserslautern: Microelectronic systems design
The project is funded by the Federal Ministry of Education and Research and is accompanied by the German Aerospace Center (DLR). The duration of the project is three years.
|
Creonic Hot IP
Related News
- Creonic Participates in 6G Research Project Led by Deutsche Telekom
- Creonic Participates in Horizon 2020 EPIC Research Project
- Dolphin Design Enables Next Generation Energy-Efficient Battery-Operated IoT Devices with New IP Platforms on TSMC 22ULL Process
- Creonic Participates in H2020 "VERTIGO" Research Project
- Creonic Participates in National Research Project KI-Radar
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |