Quad patterning a possibility at 10nm, says TSMC
Rick Merritt, EETimes
10/30/2012 3:31 PM EDT
SANTA CLARA, Calif. – Quad patterning may be needed for 10-nm process technology if extreme ultraviolet (EUV) lithography is not ready in 2015 or so when Taiwan Semiconductor Manufacturing Co. expects to start early production of the technology.
That’s the view expressed by Jack Sun, chief technologist at TSMC, in a brief interview after his keynote at the ARM TechCon here Tuesday (Oct. 30). Sun said quad patterning--four passes through a lithography stepper using four different masks--was one of several options TSMC is exploring as it works on path finding for the process.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Synopsys' Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes
- Synopsys Successfully Tapes Out Broad IP Portfolio for TSMC 10-nm FinFET Process
- Synopsys Tools Achieve TSMC Certification for 16-nm FinFET+ Process and Entered 10-nm FinFET Collaboration
- TSMC Says 10nm on Track, Countering Reports
- eMemory's NeoFuse IP Verified in TSMC 10nm FinFET Process
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset