Altera Motor Control Development Framework Delivers Unprecedented System Integration, Scalable Performance and Flexibility
Drive-on-a-Chip Reference Designs, Software and IP, and Hardware Development Boards Are Included in Scalable, FPGA-Based Motor Control Design Platform
San Jose, Calif., November 12, 2012 -- Altera Corporation (NASDAQ: ALTR) today announced a new Motor Control Development Framework that delivers unprecedented system integration, scalable performance and flexibility, while at the same time significantly reducing development time and risks for motor control system designs. The framework includes a set of customizable, single and multiaxis drive-on-a-chip reference designs and a portfolio of motor control hardware development boards, coupled with a system and software design methodology, to support the diverse requirements of next-generation drive systems. Altera will demonstrate the framework at the SPS IPS Drives show in Nuremberg, Germany, in Hall 3, Stand 405 from November 27 to 29, 2012.
The framework exploits the digital signal processing (DSP) hardware and soft embedded CPU capability in Altera® Cyclone® IV and Cyclone V FPGAs, as well as the dual ARM® Cortex™-A9 MPCore™ processors in the Hard Processor Subsystem (HPS) of Altera's Cyclone® V SoC FPGAs to provide flexible and optimal hardware/software partitioning that helps designers meet their specific end-application performance needs.
“The Altera Motor Control Development Framework brings the ideal of a high-performance, drive-on-a-chip implementation to reality by combining the flexibility and performance of Altera’s low-cost silicon with productive system-level design flows for motor control applications,” said Christoph Fritsch, senior manager in the Industrial business unit at Altera. “By providing an integrated motor control solution, including tools, IP, development boards and design methodology, combined with our Industrial Ethernet and functional safety offerings, designers can rapidly build differentiated drive platforms that also easily scale to meet evolving and future system requirements.”
The Motor Control Development Framework maximizes designer productivity by providing a system-level development environment, allowing designers to use high-level software algorithms for system management and higher-level control functions integrated with accelerated low-latency control loops implemented in the FPGA. The framework supports a model-based design methodology in MATLAB/Simulink for the development of DSP-intensive motor control loops, such as those found in field-oriented control implementations. Optimal mapping to coprocessors in the FPGA and seamless integration with software running on integrated processors is achieved through Altera’s DSP Builder and Qsys system-level design tools.
Availability
The Altera Motor Control Development Framework will be available in December 2012. For more information, please visit www.altera.com/end-markets/industrial/motor-control/development/ind-framework.html.
About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com.
|
Intel FPGA Hot IP
Related News
- Intilop delivers on Altera FPGAs, their 7th Gen. industry first, Full TCP, UDP & IGMP Hardware Accelerator System with Dual 10G ports for all Hyper Performance Networking Systems
- Altera's Quartus II Software Version 10.0 Delivers Unprecedented Performance and Productivity for High-End FPGAs
- Altera's Stratix IV GX FPGAs Deliver Unprecedented Performance for Sumitomo Electric Industries' LDPC System
- Corigine Delivers a Next-Generation Prototyping System for ASIC and Pre-Silicon Software Development
- New Cadence Tensilica FloatingPoint DSP Family Delivers Scalable Performance for a Broad Range of Compute-Intensive Applications
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |