Creonic Joins Aldec UNITE Partner Programme and Accelerates the Development of its IP Cores with Aldec Linting and Advanced Verification Tools
Basingstoke, United Kingdom – November 14, 2012 - Aldec Europe is pleased to announce that fast-growing, Germany-based IP provider Creonic GmbH, active in the field of wired and wireless communications, has joined Aldec’s UNITE™ Programme as an IP Partner.
As a member of the programme, Creonic guarantees its customers interoperability with Aldec’s EDA tools - most notably Active-HDL™, Riviera-PRO™ and ALINT™ – and will offer precompiled simulation models of its IP cores; which will produce a significant gain in simulation performance.
Dr. Matthias Alles, CEO and co-founder of Creonic, comments: “We use Aldec’s solutions to accelerate the development of our cutting-edge IP cores. For example, ALINT is used heavily for design rule checking and Riviera-PRO is our chosen platform for advanced verification. We’re also a keen advocate of the functional coverage capability within the Open Source VHDL Verification Methodology (OS-VVM™), with which Aldec has strong ties.”
Creonic offers ready-for-use IP cores for many communications algorithms and the company’s areas of expertise include Forward Error Correction (e.g. LDPC and Turbo coding) and synchronization, as well as MIMO and OFDM.
Christina Toole, Corporate Marketing Manager of Aldec Inc., states: “Long-term relationships are the cornerstone of Aldec’s success, and through our UNITE™ Programme we are working with many of the industry’s most well-known vendors of EDA solutions, IP developers and training companies to benefit our mutual customers.”
Alles concludes: “Through our use of Aldec’s EDA solutions and taking advantage of the OS-VVM we’re able to ensure our IP products comply with the highest requirements in terms of quality and performance. In addition, and a most welcome benefit, the UNITE™ programme has opened up new sales avenues for our IP offerings.”
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. http://www.aldec.com/
About Creonic
Founded in 2010, and a spin-off from the University of Kaiserslautern, Germany, Creonic develops IP cores as ready-for-use solutions for several communications algorithms, such as forward error correction (LDPC and Turbo coding), synchronization and MIMO.
The company’s close collaboration with one of the leading research institutes in the field of communications ensures Creonic has access to the latest scientific findings and technologies; which are directly integrated into the company’s broad product and service portfolio to give Creonic’s customers around the world a competitive edge.
Creonic’s products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. http://www.creonic.com/
|
Creonic Hot IP
Related News
- PLDA and Aldec Announce PCI Express DMA IP Supporting Advanced Verification Tools for FPGA Development
- Tessolve Joins GlobalFoundries' Design Enablement Network Program as a Design Partner to Bring Advanced Design Solutions to Accelerate Customer Product Development
- eMemory Won TSMC OIP Partner of the Year Award for the Outstanding Development of its NVM IP on Advanced Nodes
- MIPS Selects Imperas for Advanced Verification of High-Performance RISC-V Application-class Processors
- SmartDV, Aldec Partner to Link SmartDV's Verification IP with Aldec's Riviera-PRO Simulator
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |