English
Creonic Announces MMSE MIMO Detector IP Core
Kaiserslautern, Germany, Dec. 10 2012 - Creonic today announced the availability of a high-efficiency MMSE MIMO detector IP core for February 2013. MIMO (Multiple Input Multiple Output) techniques are being used more and more in recent and upcoming standards since they drastically outperform traditional SISO (Single Input Single Output) techniques in terms of maximum throughput and range. This gain results from an increased spectral efficiency, lowering the overall system costs.
Today, MIMO techniques can be found in wireless as well as wired communications. Most common wireless applications are 3GPP LTE, HSPA+, and WiFi (IEEE 802.11). In wired communications domains there is powerline communication (ITU G.9963 and Homeplug AV2), as well as DSL vectoring in G.993.5 alias G.vector.
A MMSE MIMO detector is an integral part of a MIMO receiver. The Creonic MMSE MIMO detector IP core offers high throughputs even on low-cost FPGAs and is convincing with its low implementation complexity at the same time. It can be tailored to different antenna configurations such as 2x2, 2x4 or 4x4. Furthermore, different kinds of modulations are supported at run-time. These are QPSK, 16-QAM, 64-QAM, and 256-QAM.
The MMSE MIMO detector IP core can be combined with other IP cores from the Creonic product portfolio like soft-decision demapper and LDPC or turbo decoders to build fully-fledged receiver designs. Its flexibility at design-time and run-time makes it the ideal fit for all kinds of MIMO applications.
About Creonic
Creonic offers ready-for-use IP cores for several algorithms of communications such as forward error correction (LDPC and Turbo coding), synchronization, and MIMO. The product portfolio covers standards like DVB-S2, DVB-C2, WiFi, UWB, and GMR. The products are applicable for ASIC and FPGA technology and comply with the highest requirements with respect to quality and performance. For more information, please visit www.creonic.com.
Learn more about the MMSE MIMO Detector IP core.
|
||||||
Creonic Hot IP
Related News
- Creonic GmbH Introduces Fast Fourier Transform IP Core
- Creonic GmbH Joins the Science and Innovation Alliance Kaiserslautern
- Creonic GmbH Introduces Advanced 5G LDPC Encoder IP core for Enhanced Mobile Broadband Connectivity
- Creonic Expands Satellite IP Core Portfolio with DVB-S2X Multi-Carrier Demodulator
- Creonic Introduces NCR Processor IP Core for DVB-S2X/DVB-RCS2 Satellite Communication
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |