Aldec Adds ARM Cortex-A9 Support to HES-7 ASIC Prototyping Platform
Henderson, NV - December 10, 2012 – Aldec, Inc., in its commitment to support the growing requirements of hardware and software verification engineers, now supports ARM® dual-core Cortex™-A9 MPCore® application development and verification in its HES-7™ ASIC prototyping platform. HES-7 leverages Xilinx Virtex-7 2000T and Zynq™-7000 All Programmable SoC and includes peripherals supporting media interfaces, memories and additional connectors to expand the development of a wide array of SoC applications.
The HES-7 ASIC prototyping platform, coupled with open-source Linux, Android and FreeRTOS solutions available from Xilinx, provides software developers of ARM Cortex-A9 applications with a complete SoC platform. These applications, along with the 4 to 96 million ASIC gate scalable capacity of HES-7, deliver a powerful verification platform for design teams comprised of hardware and software engineers.
Leverage Cortex-A9
Designers can now leverage the serial processing capabilities of the Cortex-A9 processor for applications that require intensive computations and operating systems with the parallel processing capabilities of HES-7 ASIC prototyping platform to create applications across a diverse range of markets including: Video, Communications, Control Systems and Bridging.
Applications Enabled by: | ||
Market | HES-7™ | ARM® Cortex™-A9 |
Video | Video/Image Capture and Processing Signal Encoding/Decoding Algorithm Implementation | Operating System Graphic Overlay Analytics and Manipulation |
Communications | Data Conversion Digital Pre-Distortion Connectivity | Operating System Real Time Processing Parameter Updates |
Control Systems | Data Acquisition Position Computing Human Machine Interface & Graphics | System Interface & Control Floating Points Processing Diagnostics |
Bridging | Image Capture & Processing Graphical User Interface Signal Encoding/Decoding | Image Analysis Motor Vector System Interface & Control |
Essential SoC Peripherals
New SoC Peripherals provide designers the ability to interface real-world stimuli to the design-under-test (DUT) on the HES-7 ASIC prototyping platform. Users can utilize gigabit Ethernet transceivers to develop networking applications, WLAN 802.11 b/g/n and Bluetooth® v2.1 to develop wireless systems, or High Performance HDMI Transmitter to develop home entertainment products. Memories and connectors provide additional data storage for read/write capability of today’s popular memory interfaces, and the ability to connect external hardware with the HES-7.
Availability
HES-7 with ARM Cortex-A9 support is available today with an industry-leading 1 year limited warranty. All current HES-7 customers with a dual-FPGA configuration will be provided the enhanced ARM Cortex-A9 daughterboard support with additional peripherals at no additional cost. Customers with single-FPGA HES-7 will receive the essential SoC peripherals daughterboard at no additional cost.
For Technical Specifications and more on the HES-7 ASIC Prototyping Platform along with its enhanced capabilities, please visit www.aldec.com/products/HES-7.
Prototyping with HES-7
- Available in a scalable capacity from 4 to 96 million ASIC gates
- Single and Dual FPGA Configurations Reduce Complex Partitioning
- Non-Proprietary daughterboard connectors
Support for Xilinx Zynq
- Utilize ARM dual-core Cortex-A9 MPCore Microprocessor
- Maximum Frequency of up to 1 GHz
- Enhanced with NEON Extension and Single & Double Precision Floating point unit
- 32 kB Instruction & 32 kB Data L1 Cache
- Integrated processing platform with FPGA logic reduces bill-of-material (BOM) up to 40
- Free open-source Linux, Android, and FreeRTOS solutions available from Xilinx
Essential SoC Peripherals Included
- Media Interfaces – Ethernet PHY 10/100/1000, Wi-Fi and Bluetooth, USB 2.0 DEVICE, USB 2.0 HOST, USB 2.0 OTG, HDMI, and Audio Codec (Stereo Speaker and MIC Interfaces)
- Memories – SD Socket, SPI Flash, I2C Flash, NAND Flash, SO-DIMM DDR2
- Connectors – ARM Debug, RS232, I2C, SPI, and GPIO
- Additional 4x DDR3 Memory peripheral included with Xilinx Zynq
About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
|
Related News
- Aldec Verifies Compatibility of Northwest Logic's PCI Express Cores with HES-7 SoC/ASIC Prototyping Platform
- Aldec Announces HES-7, the Largest Off-The-Shelf Xilinx Virtex-7 FPGA Prototyping System at up to 288 Million ASIC Gates Capacity
- Aldec Enters the ASIC Prototyping Market with HES-7
- MachineWare announces new ARM processor simulation and SystemC profiling products, adds Windows support
- Open-Silicon Implements Arteris FlexNoC Interconnect IP in ARM Cortex-A9 ASIC
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |