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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Report: TSMC confirms U.S. wafer fab site hunt
Peter Clarke, EETimes
12/20/2012 4:37 AM EST
LONDON – Amid plans to increase capital spending to a record $9 billion in 2013, Taiwanese foundry TSMC is seeking a location for a wafer fab, with the U.S. as a possibility, according to a local news report.
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