Qualchip Passed the Acceptance Inspection of CEC Specialist Group under Teledyne LeCroy's Test Platform's Verification
December 28, 2012 -- WuXi,China -- The USB3.0/2.0 Combo PHY IP Core Self-developed by Qualchip Technologies, Inc.(Qualchip) passed the Acceptance of CEC Specialist Group by Teledyne LeCroy's Test Platform's Verification, the performance of which were totally satisfied with USB 3.0 Physical Test Specification and USB IF(USB Implementers Forum) compliance test requirements. Moreover, most parameters were well better than the requirements of the specifications. Currently, Qualchip is porting the Combo PHY to SMIC 40LL process, which will be taped-out in January, 2013.
"The test and verification of our USB 3.0 PHY used Teledyne LeCroy's USB 3.0 total test solution based on SDA825Zi-A+PeRT3+QualiPHY. The solution combined the oscilloscope、Protocol Enabled Receiver and Transmitter Tolerance Tester with the automatic Qualify compliance software, which can complete all the items test the USB 3.0 specification requires such as physical parameters、jitter tolerance", said Mr. Jianyu Gu, the President of Qualchip, "We had already built the Joint Laboratory with Teledyne LeCroy, equipped with complete test instruments such as high bandwidth oscilloscope、BER、Signal Integrity Analyzer、SATA/SAS/USB/PCIE Protocol Analyzer and so on, which can satisfy the measurement and verification requirements of many high speed interfaces include USB 3.0/USB 2.0. The Joint Laboratory will be open to external, we are glad to provide diversified service for our customers and partners!"
The USB 3.0 solution of Teledyne LeCroy used the new generation Zi series high performance oscilloscope, especially used the PeRT3(Protocol Enabled Receiver and Transmitter Tolerance Tester) specially developed for the high speed interfaces such as USB3.0/SATA/SAS/PCIE , which made the two key difficulties getting very easy: One is how to change the various patterns for the physical transmitter test, the other one is how to let the DUT enter Loopback mode required by Receiver Jitter Tolerance Test. Therefore, the USB 3.0 solution of Teledyne LeCroy had been used popularly by USB 3.0 chip companies、system companies, which is the first choice in the industry.
About Qualchip
Qualchip is a corporation who provides high-end analog/digital IP, SoC design and production services. With the consistent goal of "Direct Volume Production Success", Qualchip licenses their own superior IP and provides the whole or partial services from “SPEC definition” to “CHIP delivery”. Qualchip had already developed many IP products with advanced technology successfully such as USB 3.0/2.0 PHY、various high performance ADC/DAC、PLL、DDR PHY. Moreover, the company also possessed complete RTL-to-GDS design flows, include hundred million of gates level and large-scale hierarchical design flow with advanced low power. The technology of IP and SoC design service of Qualchip covers the mainstream technology nodes including 28nm, 40nm, 65/55nm, 90nm, and 130nm.Welcome to log in www.qualchiptech.com to know more about Qualchip.
About LeCroy
LeCroy Corporation is a worldwide leader in serial data test solutions, creating advanced instruments that drive product innovation by quickly measuring, analyzing, and verifying complex electronic signals. The Company offers high-performance oscilloscopes, serial data analyzers, and global communications protocol test solutions used by design engineers in the computer and semiconductor, data storage device, automotive and industrial, and military and aerospace markets. LeCroy’s 48-year heritage of technical innovation is the foundation for its recognized leadership in “WaveShape Analysis”—capturing, viewing, and measuring the high-speed signals that drive today's
information and communications technologies. LeCroy is headquartered in Chestnut Ridge, New York. Company information is available at http://www.teledynelecroy.com.
|
Related News
- Introducing USB 3.0, PCIe 2.0 and SATA 3.0 Combo PHY IP Cores to empower Next Gen Connectivity Chipsets
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores with Superfast speed and High-power efficiency for lag-less data processing is Silicon Proven and available in 8nm LPP for licensing
- Mobiveil Announces Compute Express Link (CXL) 2.0 Design IP, Successful Completion of CXL 1.1 Validation with Intel's CXL Host Platform
- Synopsys Announces Industry's First CXL 2.0 VIP Solution for Breakthrough SoC Performance
- UMC Announces 22nm Technology Readiness Following Silicon Validation on World's Smallest USB 2.0 Test Vehicle
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |