GLOBALFOUNDRIES and Samsung Support New Cadence Virtuoso Advanced Node for 20- and 14nm Processes
SAN JOSE, Calif. -- Feb 5, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that two of its major foundry partners—Samsung Foundry and GLOBALFOUNDRIES—are supporting new Cadence® custom/analog technology targeting designs at the advanced nodes of 20 and 14 nanometers. The two foundries are providing SKILL-based process design kits (PDKs) for the newly introduced Cadence Virtuoso® Advanced Node.
“Moving to 20 and 14 nanometers presents numerous new manufacturing challenges, so we have been working closely with Cadence to help our mutual customers over the hurdles,” said Andy Brotman, vice president, Design Infrastructure at GLOBALFOUNDRIES. “Providing PDKs that meet customer demand for features like native SKILL PCells and real-time dynamic coloring is an essential element for the ecosystem to develop the foundation IP necessary to bring these new technologies to designers.”
“Manufacturing designs at Samsung’s 14-nanometer process requires advanced technology and methodologies that can tackle new requirements like double patterning and FinFETs,” said Dr. Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Device Solutions at Samsung Electronics. “With the Samsung-developed new SKILL-based PDK for our 14-nanometer process node, our customers can now improve design start-up time, boost designer productivity, and improve design quality.”
Virtuoso Advanced Node addresses the toughest challenges facing engineers, including layout-dependent effects (LDEs), double patterning, color-aware layout and new routing layers. The new technology integrates seamlessly with the Cadence Integrated Physical Verification System (IPVS) —technology for DRC and DPT checking — to conduct on-the-fly checks that reduce layout iterations.
“Virtuoso Advanced Node provides many new functionalities to enable our customers’ designs at the most advanced nodes of 20 and 14 nanometers,” said Dr. Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. “And with their SKILL-based PDKs for these new process nodes, our foundry partners continue to provide the enablement necessary to ensure these complex designs will be successfully and profitably manufactured.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
- Cadence AI-Based Virtuoso Studio Certified for Samsung Foundry PDKs for Mature and Advanced Nodes
- Samsung Foundry Certifies Cadence Virtuoso Studio Flow to Automate Analog IP Migration on Advanced Process Technologies
- Cadence Announces Broad Next-Generation Memory Standard Support in Samsung Foundry's Advanced Process Technologies
- Cadence Physical Verification System Certified for GLOBALFOUNDRIES 65nm to 14nm FinFET Processes
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |