OneSpin Solutions Adds RTL-to-RTL Equivalence Checking to Product Family
360 EC-RTL Features Robust Register, Sequential Checking, Power Optimization Verification Options
MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) solutions, announced immediate availability of 360™ EC-RTL, equivalence checking software that compares revisions of register transfer level (RTL) code.
360 EC-RTL is part of the OneSpin 360 EC Product Family. An RTL-to-RTL equivalence checker used to exhaustively compare two revisions of synthesizable RTL code, it features robust register, sequential and power optimization verification.
“Our formal verification solutions now span the entire SoC design project and can be used by system integrators, verification engineers and designers,” notes Dr. Raik Brinkmann, OneSpin Solutions’ president and chief executive officer.
Introducing 360 EC-RTL
OneSpin’s 360 EC-RTL compares two revisions of synthesizable RTL code without the need for testbenches or simulation vectors. It checks register optimizations for duplication, merging, removal of constant flop and movement across hierarchies. A re-encoding feature eliminates the need for a user to re-input finite state machine (FSM) encoding knowledge.
360 EC-RTL supports Verilog, SystemVerilog and VHDL, automatically handling duplicate, merged and constant registers. Output formats can be either a log file when used in batch mode or a graphical user interface with source view, schematic and driver/load tracing. The tool can be used to revise IP and RTL code and to compare VHDL and Verilog versions of an IP block.
To employ the tool, a verification engineer inputs the golden Verilog, SystemVerilog or VHDL RTL code, as well as the modified RTL code to run the equivalence checker. The tool then automatically compares the new RTL code with the golden RTL code. If the code is modified, the modified version would be entered as well and run through the equivalence checker. The tool would automatically compare the new RTL code with the golden RTL code.
The OneSpin Solutions Product Portfolio
OneSpin Solutions provides comprehensive formal verification solutions across the entire system-on-chip (SoC) design project. Its software is in use on application specific integrated circuit (ASIC) and field programmable gate array (FPGA) designs to reduce verification effort and costs and deliver high functional quality.
The OneSpin 360 EC Product Family is an automated verification solution to show the functional equivalence of design representations. It can be used standalone for full-chip implementation design equivalence in both ASIC and FPGA flows or in conjunction with the OneSpin 360 DV Product Family to preserve design quality through subsequent implementation and optimization phases. (See accompanying news release also issued today titled, “OneSpin Solutions Unveils OneSpin 360 DV Product Family.”)
The OneSpin 360 DV Product Family covers the full spectrum of formal ABV applications, from push-button automatic RTL analysis to OneSpin’s unique GapFreeVerification™. OneSpin 360 DV accelerates a variety of verification tasks, shortens verification schedules and enables engineers to achieve a design quality that cannot be ensured by any other functional verification approach. It enables step-by-step learning, making new users productive in days.
The OneSpin Product Family will be demonstrated February 26-27 from 3:30 p.m. until 6:30 p.m. at DVCon 2013 at the Doubletree Hotel in San Jose, Calif. Details about DVCon can be found at: www.dvcon.org.
Availability
OneSpin’s 360 EC-RTL is shipping now. Pricing is available upon request.
For more information, visit www.OneSpin-Solutions.com.
About OneSpin Solutions
Electronic design automation (EDA) supplier OneSpin Solutions of Munich, Germany, was founded in 2005 as a spin-off from Infineon Technologies AG. It leverages more than 300 engineer-years of formal verification technology development and application service experience to enable design teams to avoid costly redesigns and respins, while dramatically cutting their verification effort and costs and time-to-market pressures. Market-leading telecommunications, automotive, consumer electronics, and embedded systems companies rely on OneSpin to reduce their verification effort and achieve the industry’s highest possible verification quality. Email: info@onespin-solutions.com. Website: www.onespin-solutions.com.
|
Related News
- OneSpin Solutions Delivers First Equivalence Checker Dedicated to FPGA Synthesis Verification
- Quadric's 3rd Generation Chimera GPNPU Product Family Expands to 864 TOPs, Adds Automotive-Grade Safety Enhanced Versions
- Truechip Adds New Customer Shipments of Verification IPs For RISC-V Family Including TileLink
- CAST Adds Switched TSN Endpoint Controller to Time-Sensitive Networking Ethernet IP Cores Family
- Cadence Introduces the Conformal Smart Logic Equivalence Checker
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |