NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
A look inside Cadence's IP core strategy
Rick Merritt, EETimes
3/13/2013 2:01 AM EDT
SANTA CLARA, Calif.–The partnership of Lip-Bu Tan and Chris Rowen was feted at the annual CDN Live event here this week, but like all marriages it will take time for its real value to become clear.
Tan believes the future for both Cadence Design Systems Inc., which he leads, and the EDA sector as a whole lies in an integrated set of tools and configurable cores to enable next-generation systems. It’s a reasonable vision that faces a number of tests in the coming weeks and years.
First, Tan must close his acquisition of Rowen’s Tensilica Inc. to gain access to its configurable DSP and RISC cores. He also is waiting on regulators in India to OK his February bid to buy Cosmic Circuits (Bangalore), a company with much of the interface cores needed to wrap around Rowen’s processors.
Then the hard work of integrating Cadence’s tools and staff with those cores and companies begins. At that point, the tool maker will get its first shot at an intellectual property business where one rival--Mentor Graphics Corp.--ventured and failed and another--Synopsys--has a well established business.
Meanwhile, Tan will need to watch his flanks. FPGA vendors Altera Corp. and Xilinx Inc. have been amassing intellectual property cores of their own, particularly in the hot communications sector. They aim to drive chip designs to their own integrated silicon and tool sets.
As it competes with its traditional EDA and emerging FPGA rivals, Cadence also must take care not to sour its relationship with ARM Holdings plc., the world’s largest core vendor. The two companies are partners in pioneering new process technology nodes that represent the most lucrative markets for the EDA vendor.
It’s no walk in the park, but analysts are generally giving the Cadence acquisitions and strategy a cautious thumbs up--so far.
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