DI2CMS, I2C Master - Slave Bus Interface from Digital Core Design

• Master & Slave operation [support for all speeds: Standard, Fast, Fast Plus, High Speed]
• Arbitration and clock synchronization
• Support for multi-master systems
• Support for both 7-bit and 10-bit addressing formats
• User-defined timings [data setup, start setup, start hold and others]
• Simple interface with support for: AMBA – APB Bus, Altera – Avalon Bus, Xilinx – OPB Bus
• Interrupt generation and more…

The DI2CMS is technology independent, that's why a VHDL or VERILOG design can be implemented in a variety of process technologies. – Basing on 14 years’ market experience, we’ve wanted to design an I2C IP Core, which will offer maximum functionality – says Piotr Kandora, VCEO, Director of R&D in Digital Core Design – For this reason, the DI2CMS implements almost all functions available, so it can be completely customized in accordance to customer's needs.

Digital Core Design’s family of I2C IP Cores consists of: DI2CM, DI2CS, DI2CSB and the DI2CMS mentioned above. Depending on the target application, they can work as a master, slave, base or master/slave. TheDI2CM – I2C Bus controller Master – performs master communication between a microprocessor/microcontroller and an I2C Bus. It allows operations as the I2C master transmitter and the I2C Master receiver. DI2CS - I2C Bus controller Slave – carries out slave communication between a microprocessor/microcontroller and an I2C Bus. It allows operations as an I2C Slave receiver and an I2C Slave transmitter. And last but not least, the DI2CSB – I2C Bus controller Slave/Base version – performs communication between an I2C Bus and passive devices, like LCD drivers, memories etc. More information & data sheet: http://dcd.pl/ipcore/119/di2cms/

KEY FEATURES:

• Conforms to v.3.0 of the I2C specification
• Master mode:
• Master operation
• Master transmitter
• Master receiver
• Support for all transmission speeds
• Standard (up to 100 kb/s)
• Fast (up to 400 kb/s)
• Fast Plus (up to 1 Mb/s)
• High Speed (up to 3,4 Mb/s)
• Arbitration and clock synchronization
• Support for multi-master systems
• Support for both 7-bit and 10-bit addressing formats on the I2C bus
• Build-in 8-bit timer for data transfers speed adjusting
• Slave mode:
• Slave operation
• Slave transmitter
• Slave receiver
• Supports 3 transmission speed modes
• Standard (up to 100 kb/s)
• Fast (up to 400 kb/s)
• Fast Plus (up to 1 Mb/s)
• High Speed (up to 3,4 Mb/s)
• Allows operation from a wide range of input clock frequencies
• User-defined data setup time
• User-defined timing (data setup, start setup, start hold, etc.)
• Simple interface allows easy connection to microprocessor/microcontroller devices
• Interrupt generation
• Available system interface wrappers:
• AMBA - APB Bus
• Altera Avalon Bus
• Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready

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