Cadence and GLOBALFOUNDRIES Collaborate to Improve DFM Signoff for 20- and 14-Nanometer Nodes
Cadence Pattern Classification and Pattern Matching Solutions Speed Design for Manufacturing Flows by 4X for Customers’ Advanced-Node Designs
SAN JOSE, Calif., 29 Apr 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that GLOBALFOUNDRIES has collaborated with Cadence® to provide pattern classification data for manufacturing processes of 20 and 14 nanometers. GLOBALFOUNDRIES is using the Cadence Pattern Classification and Pattern Matching Solutions because they enable up to four times faster design for manufacturing (DFM), which is key to improving customers’ silicon yield and predictability.
“We have integrated Cadence pattern classification technologies to classify yield detractors into pattern families based on pattern similarity, including inexact patterns, to maximize the efficiency of the pattern matching-based lithography signoff flow called DRC+,” said Luigi Capodieci, fellow and senior director of DFM at GLOBALFOUNDRIES. “The innovative DRC+ signoff flow has been successfully used on several 32- and 28-nanometer production IC designs, and we are now using it in today’s most advanced process geometries.”
Cadence pattern classification technology allows GLOBALFOUNDRIES to classify hundreds of thousands of yield detractor, process hotspots, and silicon failures into easily usable pattern libraries. Cadence Pattern Search and Matching Analysis are embedded in Cadence Litho Physical Analyzer, Physical Verification System and the unified Virtuoso® custom/analog and Encounter® Digital Implementation System solutions. This offers GLOBALFOUNDRIES customers the flexibility to leverage the in-design signoff pattern matching and automatic fixing available in Encounter and Virtuoso, which correlates 100 percent with the full-chip signoff flow and has successfully been used on advanced node production chips.
For GLOBALFOUNDRIES customers using Cadence design tools, the silicon-proven DFM flow is easy to use and integrates seamlessly with Cadence custom, digital, and full-chip signoff flows. The integration of pattern matching-based DRC+ into the Virtuoso Layout Suite enables a powerful, correct-by-construction methodology and enables sophisticated avoidance and auto-fixing of bad patterns. Encounter Digital Implementation System has been able to accurately and quickly find and fix 100% of the DRC+ violations without introducing additional DRC or DRC+ violations, and has been successfully used on several 28-nanometer designs.
“DFM serves as an increasingly important link between chip development and manufacturing, and can play a huge role in silicon yield and predictability,” said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “Cadence pattern classification technology helps GLOBALFOUNDRIES customers set and meet high expectations for yield, ensuring they get the highest possible return out of their complex designs. We appreciate GLOBALFOUNDRIES’ commitment to use our technology at 20 and 14 nanometers and the nodes to follow.”
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- GLOBALFOUNDRIES and Cadence Add Machine Learning Capabilities to DFM Signoff for GF's Most Advanced FinFET Solutions
- Cadence DFM Signoff Solutions Achieve Qualification for Samsung 28nm FD-SOI/14nm/10nm Process Technologies
- GLOBALFOUNDRIES and Samsung Support New Cadence Virtuoso Advanced Node for 20- and 14nm Processes
- Cadence and GLOBALFOUNDRIES Collaborate to Enable Custom/Analog and Digital Design of 20nm Manufacturing Process
- Samsung and Synopsys Collaborate to Achieve First 14-nanometer FinFET Tapeout
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |