Atrenta adds logical prototyping to analysis tool

"There are a fair amount of tools addressing the silicon virtual prototype that are concerned with addressing timing and the layout of a design," said Nurie. "What that does not address are logical and architectural issues that come at the SoC integration phase of the design process. What we are offering here is a logical virtual prototype."

"In an ideal world all IP blocks you place in a design would be matched perfectly, but the reality is blocks commonly have inconsistent clocking schemes and reset assumptions, incompatible test dependencies, and some blocks have external access requirements that can't be caught in simulation, among other problems," said Bernard Murphy, chief technical officer at Atrenta. "Users have told us they spend a significant amount of time and energy trying to work through these logical integration issues before they can even move on to the physical problems and create a silicon virtual prototype."

Users can feed Verilog or VHDL to SpyGlass SoC then use rules from Atrenta's constraints library to set up such specifics as clock hookups, resets, test and access requirements, Murphy said.

"It requires very little input because it assumes the integrator has very little knowledge of the details of a given block," he said.

SpyGlass SoC uses the fast synthesis engine of SpyGlass to obtain information about the entire SoC design and the IP blocks considered for incorporation into the SoC, Nurie said.

If the tool finds violations, it highlights the problems in the RTL to help users find the source of the problem and speed the debug process, Nurie said.

Atrenta bundles SpyGlass SoC with the base SpyGlass product at no additional charge.