inSilicon's JPEG2000 CODEC Enhances Image Compression for Embedded Applications
Improves performance of high-resolution digital cameras and mobile imaging devices
San Jose, CA , May 21, 2002 - inSilicon Corporation (Nasdaq: INSN) -- a leading provider of connectivity semiconductor intellectual property (IP), announced today the addition of the JPEG2000 CODEC to its existing portfolio of image compression semiconductor intellectual property. This imaging product is fully compliant with the ISO/IEC JTC 1/SC 29/WG 1 (ITU-T SG8) specification. The hardware based JPEG2000 CODEC targets the rapidly growing consumer, networking, and PC peripheral applications, including next-generation digital cameras, scanners, color printers, and wireless imaging devices. Compared to the previous JPEG standard, end users of these products incorporating the newer JPEG 2000 technology will benefit from improved image compression; enhanced control in trading off file size versus image quality; and greater error resiliency during image transfer in noisy environments.
JPEG2000 CODEC Features
Employing the reversible 5/3 wavelet transformation algorithms, inSilicon's JPEG2000 CODEC enables on-the fly, lossy and lossless compression and decompression operations, allowing system designers to optimize between image qualities and downloading time. Compared to traditional JPEG, the JPEG2000 CODEC has significantly crisper graphics and text, even at compression ratios exceeding 50:1.
The inSilicon JPEG2000 CODEC is portable to any ASIC or FPGA technology and is designed for embedded application implementation with very efficient gate count and low power consumption. The JPEG2000 CODEC supports programmable code block size, precinct size, decomposition levels, and quantization tables on an individual tile basis to allow for customizable compression ratios. The CODEC supports packet header coding and decoding to minimize packet-processing overhead requirements on the CPU, thereby conserving power and improving system performance. For fast system-on-chip integration to any CPU, the JPEG2000 CODEC includes a simple CPU interface providing ready access to all programmable registers.
"End-users today want faster, more efficient transfer of image files to and from portable devices. inSilicon's hardware implementation of the JPEG2000 CODEC is up to 50X faster than software-based JPEG2000 systems," said Kevin Walsh, vice president of marketing at inSilicon Corporation. "Compared to traditional JPEG systems, a complete coding and decoding JPEG2000 solution from inSilicon will enable users to process higher quality images at compression ratios beyond 50:1."
Deliverables and Availability
Hardware designers receive Verilog RTL source code, Verilog behavioral models, a comprehensive test suite, synthesis scripts, and documentation for integrating the JPEG2000 CODEC into a system-on-chip.
The JPEG2000 CODEC is available today. Contact inSilicon for pricing information.
About inSilicon
inSilicon Corporation is a leading provider of connectivity semiconductor intellectual property used by semiconductor and systems companies to design systems-on-chip that are critical components of innovative wired and wireless products. inSilicon's technology provides customers faster time-to-market, reduced risk, and lower development cost. The company's broad portfolio of analog and mixed-signal products and enabling connectivity technologies, including USB, PCI, Ethernet, IEEE-1394, JPEG, and Java™ Accelerators are used in a wide variety of markets encompassing communications, consumer, computing, multimedia, and office automation.
"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995:
The statements contained in this press release that are not purely historical are forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934. These forward-looking statements are based on management's beliefs as well as on a number of assumptions concerning future events made by and information currently available to management. Readers are cautioned not to put undue reliance on such forward-looking statements, which are not a guarantee of performance and are subject to a number of uncertainties and other factors, many of which are outside inSilicon's control, that could cause actual results to differ materially from such statements. For a more detailed description of the factors that could cause such a difference, please see inSilicon's filings with the Securities and Exchange Commission including its Annual Report on Form 10-K. inSilicon disclaims any intention or obligation to update or revise any forward-looking statements, whether as a result of new information, future events or otherwise. This information is presented solely to provide additional information to further understand the results of inSilicon.
|
Related News
- inSilicon's JPEG2000 Encoder Accelerates and Optimizes Next Generation Image Compression
- intoPIX showcases its innovative image processing and compression solutions for human & machine vision at Embedded World 2023
- Accelerate Smart Embedded Vision Designs with Microchip's Expanding Low-Power FPGA Video and Image Processing Solutions
- Imagination delivers industry's first visually lossless image compression for GPUs with a guaranteed reduction in memory footprint
- AuthenTec Enhances Embedded Security of AppliedMicro's New PacketPro Multicore Embedded Processor Family
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |