Cadence Characterization Solution for Complex Multi-bit Cells Delivers Power and Performance Benefits for Yamaha
Virtuoso Liberate and Spectre Tools Reduce Power 10% for Mobile Applications While Speeding Turnaround 2X
SAN JOSE, Calif. -- May 13, 2013 -- Cadence Design Systems today announced that it helped Yamaha Corporation reduce power consumption for its mobile consumer chips with characterization tools that delivered a 10 percent reduction in dynamic power to the clock network required for Yamaha ASICs. In addition, the Cadence® characterization solution--composed of the Virtuoso® Liberate™ and Spectre® products--provided a 2x speedup in turnaround time for characterization when compared to Yamaha’s previous technology. The benefits translate to better power performance in chips that get to market faster.
“Cadence offered the only solution capable of characterizing our complex multi-bit cells,” said Mr. Shuhei Ito, development director, semiconductor division at Yamaha. “The Virtuoso Liberate and Spectre tools were critical in helping us develop our new low-power solution and in meeting our time to market goals.”
“Yamaha’s previous technology was unable to characterize the complex multi-bit flip-flop cells required for the low-power flow Yamaha adopted,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “With its patented “Inside View” technology, the Virtuoso Liberate tools enabled Yamaha to characterize these cells automatically by eliminating the need for the user to define the functional description of the cell or specify worst-case conditions. The Cadence characterization solution meets the ease-of-use, throughput and accuracy requirements that has helped Yamaha engineers reduce power for mobile applications while cutting characterization runtimes in half.”
About Cadence
Cadence Design Systems (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- New Cadence Tensilica FloatingPoint DSP Family Delivers Scalable Performance for a Broad Range of Compute-Intensive Applications
- Synopsys Delivers Breakthrough Performance with New ZeBu Empower Emulation System for Hardware-Software Power Verification
- Cadence Launches New Tensilica DNA 100 Processor IP Delivering Industry-Leading Performance and Power Efficiency for On-Device AI Applications
- New Synopsys HPC Design Kit Delivers Superior Performance, Power, and Area Efficiency for DesignWare Embedded Vision Processor IP
- Altera PowerSoC DC-DC Step-down Converter Delivers Industry-leading Power Density, Performance and Reliability
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |