English
sureCore receives GBP250K SMART Award to prototype its low power SRAM technology
May 16, 2013 -- Today sureCore Ltd announced that it has secured a Technology Strategy Board SMART award of £250K to help realise the company’s low power SRAM technology in a leading edge next generation silicon process node. Working with the major foundries developing FDSOI and FinFET technologies the grant will be used to contribute to the development of a demonstrator chip which will be used to showcase sureCore’s patented array control and sensing scheme which significantly lowers active power consumption. Through a combination of detailed analysis and using advanced statistical models sureCore has designed an SRAM memory consuming less than half the power of existing solutions.
Paul Wells, CEO of sureCore, commented “We are pleased that the TSB has recognised the potential of our technology by awarding this grant. We have proven the technology in simulation but to fully characterise and demonstrate its benefits implementation in silicon is a must. This is a critical next step in demonstrating the value of our IP to our customers.
About sureCore
sureCore Ltd is a semiconductor IP company based in Sheffield UK focusing on low power physical IP for next generation silicon process technologies. sureCore is developing low power and variability tolerant design techniques that are applicable to a wide range of IP solutions. Initially focused on SRAM, sureCore IP will help SoC developers meet both the power and manufacturability constraints posed by leading edge process nodes. www.sure-core.com
|
||||||
Related News
- sureCore PowerMiser Low Power SRAM IP Now on Samsung 28nm FDS Process Technology
- sureCore Delivers Customised Low Power SRAM for Data Intensive Designs
- Menta Embeds sureCore Low Power SRAM IP on TSMC's 28nm Process
- Dolphin Integration Receives Open-Silicon's Award for the Emerging IP Partner of the Year 2016 in the Low Power IoT Ecosystem
- sureCore Tapes-out Low Power SRAM IP Demonstrator Chip
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
|
E-mail This Article | 
|
|
Printer-Friendly Page |