Oasys Announces RealTime Floorplan Compiler

Creates Floorplan from RTL in Days that Meets Constraints as Initial Guidance to P&R Teams

May 22, 2013 -- Oasys Design Systems announced the immediate availability of RealTime Floorplan Compiler in the Oasys RealTime suite of physical RTL exploration and synthesis tools.  Synthesis engineers, architects and RTL designers can now create a floorplan directly from the RTL that is aware of the designs dataflow and also meets timing, power, area and congestion constraints.  The resulting floorplan can then be fed forward as initial guidance to physical design teams.  Oasys RealTime Floorplan Compiler has been production proven over the last four years, but until now has not been available as a separate tool.

Reduces Time to get Initial Floorplan from 4-6 weeks to a Few Days

The ability of RealTime Floorplan Compiler to take into consideration regions, fences, blockages and other physical guidance using the advanced floorplan editing tools enables engineers to take an initially compiled floorplan from Oasys, make changes and then re-compile it with the new constraints to keep getting improved versions multiple times per day.  “One of the time consuming tasks of the SoC and ASIC design implementation phase is getting a good quality initial floorplan”, stated Scott Seaton, CEO at Oasys.   “Oasys RealTime Floorplan Compiler helps our customers reduce the cycle time for this task from 4-6 weeks down to a few days”.

Optimization at the RTL Level and Placement First Methodology

“The uniqueness of Oasys’ RealTime physical synthesis engine is that it optimizes at the RTL level utilizing a placement first methodology,” stated Paul Van Besouw, CTO at Oasys.  “This enables RealTime Floorplan Compiler to concurrently optimize RTL partitions for the designs dataflow and automatically place macros, pins and pads to come up with a high quality floorplan for the constraints given.”

Plugs into Existing Design Flows

Oasys RealTime Floorplan Compiler takes in standard synthesis inputs and physical guidance if available to create an optimized floorplan. The output is a standard floorplan DEF file which can either be fed into traditional synthesis tools or place & route tools as an initial floorplan to reduce implementation time.

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