Arasan Chip Systems introduces USB 3.0 SSIC Bridge IP
Deliverables include as high quality RTL IP, verification IP and world-wide support
San Jose, California – June 12, 2013 - Arasan Chip Systems, Inc. (“Arasan”), a leading provider of Total IP Solutions, announced today the release of its SSIC Adapter IP, supporting the USB 3.0 specification for USB Superspeed Inter-Chip (SSIC).
The SSIC IP provides low power, high speed chip to chip interconnect which leverages existing investments in USB software and system investments. High performance and reduced power are achieved by using the MIPI® M-PHY℠ as the physical layer interface. Leveraging the MIPI
M-PHY power management, the SSIC interface lowers the active power and idle power. The SSIC adapter layer IP is optimized for power, area, and EMI robustness for embedded inter-chip interfaces.
“We are known for our strong position in the SD/eMMC and MIPI IP markets, but most customers are not aware of our commitment to offering superior support”, said Andrew Haines, Vice President of worldwide Marketing at Arasan. “Support at Arasan is provided by development engineers working on the product, guaranteeing the customer will be communicating with someone who has the highest level of knowledge. This level of support is standard, regardless of where the support request is coming from.”
Arasan’s Superspeed Inter-Chip controller is a PHY adapter layer that provides a bridge between a USB 3.0 Host, Device or OTG controllers’ PIPE interface and the MIPI M-PHY RMM I interface. The Arasan USB 3.0 SSIC controller interfaces directly to Arasan’s MIPI M-PHY IP to implement the SSIC adaptation to the USB 3.0 PIPE interface.
The Arasan USB 3.0 SSIC controller is compliant with the “Super Speed Inter-Chip” supplement to the USB revision 3.0 specification, version 1.0 and the MIPI M-PHY specification revision 3.0-r.03 and provides an effective data rate of up to 5.0 Gbps per lane over 1 to 4 lanes of M-PHY. The Arasan USB 3.0 SSIC controller interfaces to the USB 3.0 Device or Host controller with PIPE3 interface at 8/16/32-bit data width.
Availability
The Arasan SSIC controller is available now and is licensed as RTL or as GDSII when delivered with Arasan’s Type 1 M-PHY. The deliverables include verification IP and world-wide support.
About Arasan
Arasan Chip Systems is a leading provider of Total IP Solutions for mobile storage and connectivity applications. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for MIPI, USB, UFS, SD, SDIO, MMC/eMMC, UFS, and many other popular standards. Arasan’s Total IP products serve system architects and chip design teams in mobile, gaming and desktop computing systems that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.
Unlike many other IP providers, Arasan’s Total IP Solution encompasses all aspects of IP development and integration, including analog and digital cores, hardware development kits, protocol analyzers, validation IP and software stacks and drivers and optional architecture consulting and customization services. Based in San Jose, CA, USA, Arasan Chip Systems has a 18 year track record of IP and IP standards development leadership.
|
Arasan Chip Systems Hot IP
Related News
- SiBEAM Introduces USB 3.0 802.11ad Reference Design Delivering Wireless Connectivity at Multi-Gigabit Speeds
- Silicon Motion Introduces the SM3267 Ultra High-Performance, Cost-Effective USB 3.0 Controller
- Renesas Electronics Introduces USB 3.0 Hub Controller with Industry-Leading Low Power Consumption and Small Mounting Area
- Aizyc Technology introduces USB 3.0 Device IP with a production worthy USB 3.0 to Gigabit Ethernet application
- SMSC Introduces Industry's First 7-Port USB 3.0 Hybrid Hub Controller Family
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |