Synopsys Delivers 2X Speedup for Implementing and Verifying Functional ECOs
New Formality Ultra Extends Equivalency Checking to Accelerate Design Closure
MOUNTAIN VIEW, Calif., June 17, 2013-- Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced Formality Ultra, a new configuration of the Formality equivalency checking solution. Formality Ultra includes innovative matching and verification technologies to efficiently guide designers through the implementation of functional ECOs with minimal impact to the design and verify the correctness of the ECOs in minutes for multimillion instance designs. These new capabilities will help designers cut in half the time they spend implementing ECOs late in the design cycle and result in shorter, more predictable schedules.
Complex designs often undergo multiple functional ECOs late in the design process due to changing specifications and functional errors. Each ECO change can adversely impact schedule and predictability of design closure, which causes designers to invest days trying to minimize the impact of every change to the design. This process can add weeks in the late stages of the design cycle.
"With the new ECO capabilities in Formality Ultra, we can cut in half the time needed for implementing functional ECOs and shorten our design schedules," said Bruce Fishbein, vice president of NCD IC Engineering at Cavium Inc. "It will also enable us to implement more complex functional changes as ECOs rather than wait for the next derivative of the design. We are planning to deploy Formality Ultra on our next project."
The new Formality Ultra adds advanced matching techniques that visually highlight the mismatch between the RTL and netlist representations of a design, allowing designers to efficiently zoom in on the changes required to implement an ECO. In addition, a new multi-point verification technology very quickly checks multiple changes made to the design enabling designers to verify the correctness of their ECOs in a matter of minutes on multi-million instance designs.
"Designers worldwide rely on Formality's equivalency checking technology to verify their complex, high-frequency designs without sacrificing chip performance or design schedules," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "Formality Ultra extends this technology to address another key challenge they face – functional ECOs. It enables designers to significantly reduce the time and effort required to implement those ECOs, increase schedule predictability and close their designs on time."
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, its software, IP and services help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at http://www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Synopsys' CustomSim Delivers 2X Circuit Simulation Speed-up
- Synopsys Delivers Platform Architect Ultra to Enable the Next Wave of AI SoCs
- Synopsys' IC Validator Signoff Physical Verification Delivers 2X Memory Reduction in Latest Release
- Synopsys' New DesignWare Sensor and Control IP Subsystem Delivers Ultra Low Power Sensor and Control Processing for SoCs
- Centaur Technology Deploys Synopsys' Formality Ultra to Shorten Design Schedules by Weeks
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |