Cadence Solutions Enable Successful Tape Out of 20-Nanometer SoC Test Chip by Global Unichip Corporation
Cadence Encounter Digital Implementation System and Cadence Litho Physical Analyzer Reduce Risk and Shorten Design Cycle
SAN JOSE, CA-- Jul 9, 2013 -- Cadence Design Systems, a leader in global electronic design innovation, today announced that the design services company, Global Unichip Corporation (GUC), utilized the Cadence Encounter Digital Implementation System (EDI) and Cadence Litho Physical Analyzer to successfully complete the tape out of a 20nm system-on-a-chip (SoC) test chip. Engineers from the two companies collaborated closely using the Cadence solutions to overcome implementation and DFM verification challenges to complete the design.
During development, GUC utilized the Cadence Encounter solution to support all of the complex steps in a 20nm place and route flow, including double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post route optimization. GUC also utilized Cadence Litho Physical Analyzer for DFM verification, turning the uncertainty of 20nm process variations into predictable impacts that helped reduce the design cycle.
"We selected Cadence as a partner for this development because of their proven success at advanced nodes," said Kevin Tseng, Director of design methodology division at GUC. "The successful tape out of this 20nm SoC test chip on a TSMC process is a direct result of our close collaboration and the capabilities of the Cadence Encounter and DFM solutions."
"As customers move to 20nm, they are faced with new challenges such as double patterning and process variations that greatly increase risk," said Dr. Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. "Cadence has addressed these advanced node challenges in both our implementation as well as DFM verification tools. The company is working closely with partners to validate these new flows to reduce risk and make it easier for customers to move to the 20nm process node with confidence."
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Hot IP
Related News
- Global Unichip Corporation Utilizes Cadence Analog IP to Implement WiGig-Enabled SoC on 28nm Process
- Cadence Announces STMicroelectronics has Taped Out 20-Nanometer Test Chip Using Cadence Tools
- GUC and Omni Design Tape Out 16nm LiDAR SoC
- Global Unichip Corporation Deploys Cadence Clarity 3D Solver to Achieve 5X Speedup of Systems Analysis for 112G Long-Reach Network Switch
- Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
Breaking News
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- YorChip announces patent-pending Universal PHY for Open Chiplets
- PQShield announces participation in NEDO program to implement post-quantum cryptography across Japan
Most Popular
- Qualitas Semiconductor Signs IP Licensing Agreement with Edge AI Leader Ambarella
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura's Cyberthreat Intelligence Tool
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Alchip Opens 3DIC ASIC Design Services
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
E-mail This Article | Printer-Friendly Page |