Cadence Delivers Verification Productivity Boost For Complex SoC Designs Through Commitment to Industry Standards

Introduces Assertion-Based Verification Technology Based on Accellera Sugar Language; Adopts Open-Source SystemC for Design and Verification

San Jose, Calif., May 28, 2002: Cadence Design Systems, Inc. (NYSE: CDN), the world's leading supplier of electronic design products and services, today enhanced its Verification Cockpit offering with new Assertion-Based Verification (ABV) technology supporting the Sugar 2.0 Accellera standard language. Cadence also announced SystemC open language support, for design and verification in its NC-Sim and open-source TestBuilder products. These moves demonstrate the company's commitment to improve design productivity through solutions based on industry standards and open interfaces.

"Our ABV capability can help digital design engineers detect and eliminate errors earlier in the verification process," said Rahul Razdan, vice president and general manager of the Cadence System and Functional Verification Group. "SystemC support can efficiently bridge the gap between complex system design, and hardware/software implementation and verification."

As part of Verification Cockpit, ABV functionality includes Sugar 2.0 assertion language support, extended transaction-based analysis and debug, and new static-checking capabilities. This combination enables designers to capture specifications, requirements, and assumptions as assertions; verify them statically using static-check techniques, or dynamically using Cadence's industry-leading mixed-language simulator, NC-Sim; detect internal errors at or near their source; and record assertion activity as transactions in the same form as those already recorded from TestBuilder, Verilog and VHDL testbenches. The net result can be efficient, comprehensive transaction-based functional coverage analysis in a unified debug environment.

Available this fall with ABV capability, Verification Cockpit configurations will vary according to customer needs. Pricing starts at $25,000.

Native support of SystemC in the Cadence® NC-Sim simulator will enable designers to mix SystemC, RTL, and analog mixed-signal descriptions. Designers also can view waveforms and hierarchy; control their C/C++, Verilog and VHDL code; and easily debug in a powerful environment that offers mixed simulation of SystemC, Verilog, Verilog-A, VHDL and VHDL-A open languages. Cadence supports TestBuilder verification extensions to SystemC 2.0. These enable designers and verification engineers to write reusable testbenches quickly and concisely at a high level of abstraction in C/C++.

"Cadence is working closely with the SystemC Verification Working Group and has proposed inclusion of verification extensions in SystemC," said Eshel Haritan, engineering group director, Systems and Functional Verification Group at Cadence. "The ability to verify SystemC transaction-level models and reuse the testbench for RTL verification can speed time to market and eliminate the error-prone task of creating a new RTL testbench."

SystemC simulation products will be available this fall, priced from $15,000.

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, California, and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services are available at www.cadence.com.

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