Allegro DVT improves its HEVC Decoder silicon IP with 10 bit support
Grenoble, France, July 19, 2013 -- Developed to compress 4K and high resolution video contents, the next generation video standard: HEVC/H.265 brings fifty percent bitrate saving compared to content encoded with H.264/AVC.
Requirement of TV broadcasting for carrying 4K and ultra-high definition content is now driving the adoption of the HEVC (High Efficiency Video Coding) standard.
This demand for devices supporting HEVC is growing fast, and Allegro DVT is ready with the industry’s first fully compliant HEVC decoding IP that supports both Main and Main10 profiles. The Main10 profile was specifically designed to improve 4K content video quality thanks to 10 bit color depth support.
Our HEVC Decoding IP is available today, runs real-time on FPGA and can be immediately delivered to any customer wishing for 4K enabled products. We see that 4K content will drive the market of next-generation ultra HD television displays (UHDTV) and content capture systems. Our customers have an immediate requirement for HEVC into System on Chip (SoC), which we are ready to address with our HEVC Decoding IP.
One of the major innovations in the HEVC standard, is the introduction of several tools to parallelize processing, such as “dependent slices”, “tiles” and “wavefront parallel processing”. Our HEVC Decoding IP is based on a scalable and unique multi-core architecture, supporting any combination of these parallel processing tools. This unique decoder architecture removes all constraints on the encoders and ensures interoperability with all types of parallelized encoding.
The HEVC Decoding IP core is designed to be easily integrated in all next generation SoC devices requiring exceptional performance while maintaining a very low operating frequency and high level of power savings.
For information or a live demonstration of our HEVC Decoder IP, please contact us at info@allegrodvt.com.
Read more on Allegro DVT products for IC vendors
Allegro DVT is a leading provider of H.264/MPEG-4 AVC|SVC|MVC and HEVC/H.265 solutions, including industry standard compliance test suites, H.264/MPEG-4 AVC and HEVC/H.265 encoder, codec and decoder hardware (RTL) IPs; and multiscreen encoders and transcoders. Allegro DVT products have been chosen by more than 100 major IC providers, OEMs and broadcasters. For more information, visit Allegro DVT's Website Allegro DVT's Website or contact info@allegrodvt.com.
|
Allegro DVT Hot IP
Related News
- World's First AV1 Decoder Silicon IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
- Allegro DVT Announces the Industry's First MPEG-5 LCEVC Decoder Silicon IP
- Allegro DVT Launches the World's First Hardware-Based VVC/H.266 Decoder Silicon IP
- Allegro DVT Releases New Versions of its Encoder and Decoder IPs with Support for 12-bit sample size and 4:4:4 Chroma Format
- Allegro DVT Adds Support of 4:2:2 10-bit Video Profiles to its Multi-Format Encoder/Decoder Hardware IPs.
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |