Fab lite, Design lite
Brian Bailey
EDN (July 23, 2013)
It must have been twenty years ago when Cypress Semiconductor came up with a revolutionary business model. Before then every semiconductor company had a design team and a fab. They were totally integrated in a vertical sense. Many of them developed their own EDA tools, but that was already on the way out. It was a lot more economical to have an EDA company amortize the cost of tool development over several design houses and to allow that form of specialization. It was a difficult transition for some because standards did not exist at that time and so required the adoption of new methodologies, languages and tools. Then Cypress asked the question – why do I need a fab. They are expensive to build and maintain and require a lot of expertise that would be better handled by someone else. At the time most people thought they were crazy. The companies with the fabs would surely cut them off as soon as they had a capacity squeeze. Of course, the rest is history. Very few design houses have their own fabs these days and even Intel is basically renting out space in their fabs. This was a significant change in business model and made companies much more capital lite.
The next change was brought about by the introduction of Intellectual Property. This started with processors and a few commodity blocks. The processors took specific expertise and the commodity blocks added no value to the final product. Bringing those components in as fully designed and verified blocks saved time and money and allowed the companies to specialize even more. The lack of standards slowed the rate of adoption, and we are still working on getting all of those in place today. Over the next ten years, the number and size of the IP blocks grew and today may fill 80% or more of the chip surface area and be made up of a hundred or more instances. This again made the design houses leaner and requires less capital.
E-mail This Article | Printer-Friendly Page |
Related News
Breaking News
- Alphawave Semi Q4 2024 Trading and Business Update
- ST-GloFo fab plan shelved
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Altera Launches New Partner Program to Accelerate FPGA Solutions Development
- Electronic System Design Industry Posts $5.1 Billion in Revenue in Q3 2024, ESD Alliance Reports
- Breaking Ground in Post-Quantum Cryptography Real World Implementation Security Research
- YorChip announces patent-pending Universal PHY for Open Chiplets