Sonics boosts silicon backplane IP network

Sonics boosts silicon backplane IP network; ARM lands licensing pair

Sonics boosts silicon backplane IP network; ARM lands licensing pair
By Michael Santarini, EE Times
May 28, 2002 (1:34 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020528S0031

SANTARINI_MIKE Silicon backplane intellectual-property provider Sonics Inc. has upgraded its SiliconBackplane MicroNetwork, adding new partitioning capabilities as well as better interoperability with EDA tools in its version 2.2 release. SiliconBackplane is a quasi on-chip bus to which users attach intellectual-property blocks to create system-on-chip designs.

According to the company, the new version of the IP and accompanying development environment will allow SoC designers and architects to reduce the time-to-market of products and entire SoC families.

The new features provide support for hierarchical SoC design, reduced power consumption and more efficient functional verification, and combine to support higher SoC complexities while accelerating overall design cycle times, the company said.

The multibackplane feature allows designers to create a hierarchical subsystem partition of an SoC across multiple on-chip MicroNetworks, according to Sonics.

This provides greater flexibility for the subsystem itself and the SoC as a whole, the company noted. Multiple subsystems, each with an independent MicroNetwork clock frequency and data path width, can be connected in tree or fully connected topologies to isolate local data flows, improving total system bandwidth while reducing SoC area and power consumption, the company claimed.

The connections between MicroNetworks use the open-core protocol socket standard and do not require additional design work or glue logic.

Sonics has also added a multicast feature that allows designers to send data to multiple IP cores across one or more MicroNetworks.

Version 2.2 also includes a feature for optimizing the performance of write transfers, which are dominant in many networking applications.

Sonics has also improved the MicroNetwork graphical SoC development environment In version 2.2 to include support for Synopsys' Power Compiler and Cadence's Test Builder.

The company said it has also made other enhancements to the MicroNetwork and its development environment to improve modeling, simulation and synthesis control.

SiliconBackplane MicroNetwork version 2.2 starts at $240,000.

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ARM Ltd. (Cambridge, U.K.) has announced that Broadcom has extended its licensing agreement with ARM and will use ARM's ARM7TDMI-S core and the ARM926EJ-S core in future IC designs.

In a separate announcement, ARM announced that it has licensed its ARM7TDMI core to PortalPlayer Inc., which will use the core in its digital audio encode and playback devices.

ARM said the deal with Broadcom significantly builds upon ARM's presence in the networking and broadband sectors, though the companies declined to state in which types of designs Broadcom plans to employ the ARM cores.

The ARM926EJ-S synthesizable processor core inc orporates ARM's Jazelle technology, which ARM claims accelerates Java execution by up to 10 times compared with a fully software-based Java Virtual Machine.

Original equipment manufacturers and original device manufacturers use ARM core-based products from PortalPlayer to develop digital audio product families, from player-only portable devices to digital audio-enabled encoding and playback systems for the pocket, home and car.

PortalPlayer offers platform solutions that include an integrated SoC controller, firmware, digital media manager application software and reference designs to speed system integration.

PortalPlayer said its ARM7TDMI-based SuperIntegration SoC controllers are programmable and upgradable, which allows designers of digital audio playback and recording applications to adjust the technology as the requirements of audio entertainment evolve.