Tharas Systems extends Hammer Hardware Accelerator capacity to 128 Million Gates

A cluster of Hammer 32M Hardware Accelerators scales capacity to 64, 96 and 128 Million Gates to offer a true system level verification platform

Santa Clara, Calif -- June 3, 2002 --Tharas Systems, Inc., a provider of a new generation of hardware acceleration solutions, today announced immediate availability of its hardware-assisted verification solution that addresses system design capacities of up to 128 Million RTL Gates and 16 Giga Bytes of memory. The solution consists of an array of its recently introduced Hammer 32M, a true 32 Million RTL gate equivalent capacity hardware accelerator tightly integrated with SimCluster, a distributed parallel Verilog simulation technology from Avery Design Systems. A 2, 3, and 4 Hammer cluster solutions will be available to address 64, 96 and 128 Million RTL gate capacity configurations respectively.

"When we built our new 32M Box, we put in hooks to scale this solution for capacity and performance. We are now able to quickly deliver a distributed parallel Verilog acceleration solution by partnering with Avery Design Systems. By partitioning designs along their natural boundaries – such as line cards or ASICs, the solution even enhances overall acceleration. For example, we have observed that the same design partitioned across a 4 Hammer configuration can deliver a 3X performance improvement over a single Hammer. The addition of 2, 3 and 4 Hammer 32M cluster solutions at compelling price/performance will make capacity constraint a non-issue and we expect it to advance widespread usage of RTL hardware acceleration at complex System level verification," says Prabhu Goel, Chairman & CEO of Tharas Systems.

Hammer 128MC, a 4-cluster configuration, is priced at US$1,980,000 for 128 Million RTL gate-equivalent and 16 Giga Bytes of memory. Hammer 96MC, a 3-cluster configuration, which is capable of accelerating 96 Million RTL gate-equivalent and 12 Giga Bytes of memory, is priced at US$1,580,000. A 2-cluster Hammer 64MC is priced at US$1,280,000 and can handle 64 Million RTL gate equivalent and 8 Giga Bytes of memory. Tharas Systems will continue to offer its current non-cluster configurations of 2M, 4M, 8M, 16M and 32M – 2, 4, 8, 16 and 32 Million RTL gate-equivalent configurations respectively.

"We are partnering with Tharas using our SimCluster distributed parallel simulation technology, to expand on Hammer's leading acceleration solution for unsurpassed verification performance, capacity, and flexibility. Hammer 128M delivers the flexibility to maximize throughput by running one or more Hammer 32M nodes concurrently based on simulation target size - that's like getting 4 Accelerators in one," remarks Chilai Huang, President and CEO of Avery Design Systems.

Tharas Systems' Hammer provides Verilog simulations with the fastest compile and run times, while at the same time offering ease of use and debug capabilities comparable to that of software simulators. Compile times are as fast as 10 Million RTL gate-equivalent per hour as compared to 8 hours per Million RTL gate-equivalent for other FPGA-based systems. Run times range from 10 to 1000 times faster than software simulators. Hammer's innovative hardware architecture includes a proprietary backplane that delivers more than 10 Gbps bandwidth, minimizing run time degradation during debug – contrast this to dramatic loss of performance during run time of competing FPGA-based systems during debug.

Hammer works with existing RTL and gate-level verification environment. As a result, designers can continue to use their familiar verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (NASDAQ: SNPS) and Cadence Design Systems, Inc. (NYSE: CDN).

Hammer supports design sizes of up to 128 Million Gate-equivalent RTL code, and 16 Gigabyte in hardware. Hammer pricing ranges from US$115,000 to US$1,980,000.

 
About Tharas Systems
Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Hammer? offers a patented, next-generation hardware accelerator for Verilog simulations with the fastest compile times and run times, while at the same time offering ease of use and debugging capability comparable to that of software simulators. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com/.

Hammer is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

About Avery Design Systems
Avery Design Systems develops and markets innovative functional verification software solutions. Avery provides innovative Verilog-based functional verification products to dramatically raise productivity of the ASIC-based systems and SOC design verification process leveraging mainstream design languages and advanced verification technologies for testbench automation, functional coverage analysis, protocol verification, dynamic lint, HW-SW co-verification, and distributed simulation. Founded in 1998, Avery is privately held. Corporate headquarters is located at 2 Atwood Lane, Andover, MA 01810. Visit Avery Design Systems at http://www.avery-design.com.
 

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