Mentor Graphics New QuickUse IP Repository Chosen by Agere Systems
WILSONVILLE, Ore.--(BUSINESS WIRE)--June 5, 2002--Mentor Graphics Corporation today announced the availability of its QuickUse(TM) Repository, an off-the-shelf IP (intellectual property) repository based on its proven QuickUse Development System (QDS) knowledge management infrastructure.
The QuickUse Repository provides a Web-based design data management system to enable enterprise-wide IP management, distribution and qualification for improved design reuse efficiency and product quality. Mentor Graphics also announced that Agere Systems, the world's second-ranked Application-Specific Integrated Circuit (ASIC) provider, has adopted the QuickUse Repository as the IP infrastructure for its global design teams.
To meet the demands of increasing design complexity and time-to-market pressures, system-on-chip (SoC) designers must rely on pre-configured design components. As a result, companies have growing libraries of IP representing significant investment in both design time and resources. However, without organized management, this IP investment may be inaccessible on individual hard drives or lost in backup archives, making effective design reuse impossible. The QuickUse Repository provides a centralized infrastructure for Web-based access to a revision-controlled library of IP and design data.
"The QuickUse Repository is the only commercially available Web-based repository that was built with the specific requirements of the SoC designer in mind," said Phil Bishop, vice president and general manager of Mentor's Consulting division. "This new offering builds on the knowledge base of our consulting organization and brings the powerful design reuse capabilities of QDS to a new group of customers who require the quick deployment of a packaged solution."
QuickUse Repository
The QuickUse Repository software is designed to maximize the success of enterprise-wide IP management. It uses a proven three-tier architecture with an Oracle database for flexible management of any type of design data. To give designers maximum flexibility, the repository is accessible three ways: through a Web browser for quick searching, comparison and download of IP; through a Java-based GUI client which allows for easy administration and maintenance; or through a command line interface for easy access through scripts or from within common EDA tools. The QuickUse Repository includes unique IP qualification capabilities to measure the IP against established industry design standards such as VSIA and OpenMORE, as well as custom design standards that can be entered into the system. The QuickUse Repository includes a full-featured API (application programming interface) to allow users to extend functionality with the addition of custom features.
"For our broad portfolio of highly integrated, system-level ASIC technologies, Agere Systems wanted an off-the-shelf software solution for IP management that would allow us to quickly deploy and begin sharing IP throughout the Agere global ASIC design team," said Jon Fields, vice president of design platforms with Agere Systems. "Our ASIC customers and design teams working with our customers both benefit from using this software solution."
Pricing and Availability
The QuickUse Repository is available immediately, with list prices starting at $450,000 for a regional server license with 25 users. The QuickUse Repository is an off-the-shelf solution that does not require consulting services for implementation, although consulting services are available for customers who require additional customization for their design environment.
About the QuickUse Development System
The QuickUse Development System (QDS) is a complete Internet-based knowledge management solution that automates IP management and SoC design processes and serves as the foundation for the QuickUse Repository. At the heart of QDS is tool-independent enterprise data and flow management software featuring an extensible core application program interface. According to the most recent market data from Gartner's Dataquest, Mentor Graphics is the EDA leader in enterprise data management solutions with 51 percent of the market(1).
About Mentor Consulting
Mentor Consulting is a leader in worldwide semiconductor intellectual property services and maintenance and a provider of innovative solutions addressing today's design and verification challenges. Its infrastructure and methodology solutions for SoC design, board process, system verification and design reuse are used worldwide by forward-looking electronics companies to optimize their design productivity and advance adoption of the latest industry design best practices. For more information on these and other services and products e-mail Mentor Consulting at mentor_consulting@mentor.com or visit www.mentor.com/consulting.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.
(1) EDA 2001: It's Good to be an EDA Vendor, Market Trends, Gartner/Dataquest. October 2001
Mentor Graphics is a registered trademark of Mentor Graphics Corporation. QuickUse is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
|
Related News
- Mentor Graphics QuickUse IP Repository Adopted by Faraday
- Mentor Graphics Automates the IP Qualification Process with the QuickUse IP Qualification System
- Mentor Graphics Inventra Launches eParts IP Repository and Delivery System
- Mentor Graphics expands formal verification's reach with new cross-platform GUI and apps for sequential logic equivalence checking and CDC gate-level analysis
- Silicon Creations Selects Mentor Graphics Software for High-Performance Analog and Mixed-Signal IP Verification
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |