KALRAY today announces world’s first hyper-scalable 1000+ cores MIMD processor architecture for next generation exaflop supercomputers.
SC13 Denver -- Nov. 19, 2013 -- KALRAY today announces world’s first hyper-scalable 1000+ cores MIMD processor architecture (about 1 TeraFlops at less than 30 Watts, and up to0.5 TeraBytes of DDR) for Next Generation ExaFLOP Ssercomputers.
This MPPA SCoC (SuperComputer on a Chip) hyper-scalable architecture, is the only one available for next generation exaflop supercomputers. Indeed, breaking the exaflops barrier becomes realistic, thanks to its low power characteristics and the NoC extension (NoCX).
Typical applications include :
- Oil and Gas (e.g. RTM (i.e. Reverse Time Migration) and FWI (i.e. Full Waveform Inversion algorithms),
- Finance (e.g. MapReduce based Monte Carlo or Black-Scholes options pricing and HFT (i.e. High-Frequency Trading) algorithms with possible
- FPGA & MPPA mixed architectures),
- Numerical Simulations (e.g. CFD (i.e. Computational Fluid Dynamics)),
- Video (e.g. Transcoding, Encoding and Decoding),
- Cloud based Services (e.g. Video Security and Augmented Reality),
- Data Security (e.g. Cryptography and Homomorphic Encryption),
- Storage (e.g. Seismic Loss Less compression),
- Biology (e.g. Genome DNA Sequencing) and
- Big Scientific Instruments.
This disruptive KALRAY’s massively parallel processor has low power, scalable and deterministic characteristics which makes it the best suitable solution for embedded intensive computing.
It minimizes the TCO (i.e. Total Cost of Ownership) both by reducing CAPEX (i.e. Capital Expenditures) & OPEX (i.e. Operating Expenses), thus maximizing the total ROI (i.e. Return On Investment).
By connecting 4 MPPA boards, this setup totalizes 1152 MIMD cores and 32 GigaBytes of DDR, expendable to 512 GB.
Additionally, MPPA ACCESSCORE, KALRAY’s SDK, allows upward compatibility from the MPPA-256 to a multiple MPPA MANYCORE setup. The demonstration for the show runs an FFT algorithm scaling on to 1000+ cores. This setup develops about 1 TeraFlops but consumes less than 30 Watts and has 32 GB of DDR (expendable to 0.5 TeraBytes).
Kalray recently announced an office in the USA, in addition to the existing European & Japanese offices.
ABOUT KALRAY
KALRAY is a fabless semiconductor & software company developing and selling a new generation of manycore processors for high performance applications . Our products boost the development of innovative digital applications in the fields of image and signal processing, telecommunication, intensive computing , industrial automation , data management , or transport .
|
Related News
- Tensilica Announces Availability of Atlas Reference Architecture Dataplane Processors for a Complete Baseband PHY for LTE, HSPA+ and WiMAX
- C-DAC partners with MosChip and Socionext for design of HPC Processor AUM based on Arm architecture
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- RED Semiconductor announces VISC™ licensable high performance processor architecture for RISC-V
- Tachyum Books Purchase Order to Build System with 25,000x ChatGPT4 Capacity and 25x Faster than Current Supercomputers
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |