oViCs Introduces 4Kp120 HEVC/H.265 Decoder
Saratoga, CA -- January 15, 2014 -- oViCs, a leading provider of advanced video IP cores, today introduced ViC-1, the world's highest performance and high efficiency 4Kp120 HEVC/H.265 decoder supporting Main, Main-10, and Main Still Picture Profiles up to Level 5.2, High Tier.
The ISO/IEC HEVC/H.265/MPEG-H compression standard developed by JCT-VC, Joint Collaborative Team on Video Coding, is poised to be the next generation video compression technology to dominate the mobile, connected home, video capture, streaming, and distribution markets. ViC-1 enables SoC developers to realize fast time-to-market with an optimized HEVC solution specifically configured for their system requirements.
Ad |
HEVC/H.265 Main10 Profile Decoder IP for UHD(4K) ![]() Full HD/UHD video and vision integrated platform solution ![]() |
oViCs’ ViC-1 is a full featured, highly optimized, real-time HEVC/H.265 decoder supporting Main, Main-10, and Main Still Picture Profiles up to 4Kp120 resolution on a single instance, with or without multiple slices, tiles, or wavefront parallel processing. ViC-1 requires only 180 to 840 Kgates and 8 to 179 Kbytes of internal memory, depending on the configuration. The tiny silicon area and low clock frequency design lead to a very power-efficient solution; for instance, only a clock frequency of 72 MHz is needed for 1080p60 bitstreams.
The 4Kp120 performance envelope can be allocated to multiple streams. The entropy encoded data is processed by a hardware CABAC engine with up to 5 bins/cycle throughput, assisted by a thin software layer responsible for header processing, control, and high level error recovery. ViC-1 is specifically designed for easy integration into advanced mobile, smart TV, connected home, and automotive SOCs, where low power and low latency are important.
“We are delighted to introduce our state of the art IP to enable our customers for a quick and smooth transition to the new compression technology without impact on power consumption and overall system cost,” said Sorin Cismas, CEO of oViCs. “This will accelerate the industry adoption of the new HEVC/H.265 compression standard that reduces the bitrate by approx. 2X for both professional and user-generated content.”
About oViCs
oViCs is a startup based in Saratoga, CA, focused on developing advanced semiconductor platforms and intellectual property solutions for HEVC/H.265/MPEG-H, video processing and analysis for the mobile, automotive, connected home, video capture, streaming, and distribution markets. For more information about oViCs, please visit http://www.ovics.com.
|
Related News
- PathPartner Technology and Accelize Announce Availability of HEVC / H.265 FPGA Decoder for QuickPlay Development Platform
- AMPHION releases 2 extended performance variants of its highly successful HEVC/H.265 'Malone' video decoder IP core
- AMPHION targets DAC 2016 to demonstrate compact HEVC/H.265 hardware decoder IP using H.265 bitstreams from encoder IP innovator NGCodec
- Full-Hardware Real-Time H.265 HEVC Video Decoder Core Coming from CAST
- Realtek Licenses HEVC (H.265) Decoder from Ittiam for Next Generation Consumer Applications
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |