Altera and Synplicity Introduce Interface Standard for FPGA Physical Synthesis
Physical Synthesis Design Format Enables Closer Interoperability Between Design Tools for High-Density Programmable Logic
Design Automation Conference, New Orleans, June 10, 2002 -- Altera Corporation (NASDAQ: ALTR) and Synplicity, Inc. (NASDAQ: SYNP), a leading supplier of software for the design and verification of semiconductors, today introduced a new standard interface called PSDF, Physical Synthesis Design Format, that increases interoperability between physical synthesis and place-and-route tools. This new Altera interface, which was co-developed with Synplicity, allows for improved timing and placement information for use by physical synthesis tools. As a result of this interface, circuit performance is significantly improved while the number of design iterations is reduced when using Synplicity's Amplify® Physical Optimizer™ software, the industry's first physical synthesis tool for PLDs, and Altera's Quartus® II design software.
"Altera engineers worked closely with Synplicity's FPGA synthesis team to ensure that our software tools deliver accurate timing and placement information for customers designing high-performance system-on-a-programmable-chip (SOPC) designs," said Y.K. Ning, director of Altera's EDA software engineering. "Altera is making this PSDF standard interface format available to other EDA vendors, with the goal that it will be widely adopted across the industry." This new standard will support Altera's Stratix™, APEX™ II, APEX 20KE, APEX 20KC, and Excalibur™ devices.
"With multi-million gate programmable logic devices evolving to integrate complex functions and embedded processors, incorporating accurate timing and placement information during the synthesis process is essential to meeting aggressive timing goals quickly," said Venkatesh Nathamuni, director of engineering for Amplify and Certify products at Synplicity. "By working closely with Altera to develop a standard interface, we anticipate that SOPC designers will gain accelerated access to the Amplify software's physical synthesis technology, enabling them to take full advantage of advanced architectural features in Altera's high-density devices."
Pricing and Availability
The next available version of Altera's Quartus II design software will write out the PSDF file format for use by Physical Synthesis Tools. Synplicity's Amplify Physical Optimizer software v3.1 will support this PSDF format. The Amplify software is available as an option to Synplicity's Synplify Pro logic synthesis software.
About Altera
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.
About Synplicity
Synplicity, Inc. (NASDAQ: SYNP) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer and military/aerospace electronics systems. Recognizing the company's industry-leading position, Dataquest named Synplicity as the #1 provider of PLD synthesis tools in 2000 with a 45 percent market share. Synplicity leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs) and system-on-chip (SoC) integrated circuits. The company's fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL and Verilog) and run on popular platforms. As of March 31, 2002, Synplicity employed 269 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif. For more information on Synplicity, visit http://www.synplicity.com.
|
Intel FPGA Hot IP
Related News
- Cypress, Nuvation and Arrow Electronics Introduce New USB 3.0 SuperSpeed Interface Board for Altera FPGAs
- Macnica Releases SLVS-EC Interface IP Core for FPGA
- Xilinx and Micron Demonstrate Industry's First Hardware Interoperability of FPGA and RLDRAM 3 Memory Interface Standard
- Altera Charts New Course for the Industry with Optical Innovation
- Mentor Graphics Announces Logic and Physical Synthesis Support for Xilinx 7 Series FPGAs
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |