IBM sets new standard for custom chip designs
Cisco Systems expected to be the first to use
East Fishkill - June 10, 2002 - IBM today announced the industry's most advanced custom chip capability.
The new IBM application-specific integrated circuit (ASIC) offering, called Cu-08, supports circuits as small as 90 nanometers (a nanometer is a billionth of a meter), as well as innovative materials and design techniques to drive power consumption down by as much as 40 percent while pushing performance up as much as 20 percent.
"IBM understands that customers don't just want new technology; they want a supplier with the experience and resources to help them use it," said Michel Mayer, general manager, IBM Microelectronics Division. "It's going to take more than just smaller geometries. It's going to take technologies like copper and low-k; design innovations like embedded DRAM and low-power transistors; and knowledge of the customer's business and applications to best apply them all."
Cisco Systems, the worldwide leader in networking for the Internet, is one of IBM's ASIC customers and is expected to be the first to use this new technology in the development of its next-generation products. With IBM's earlier generation of ASIC technology, called Cu-11, the company worked with Cisco to implement a single chip supporting more than 35 million "gates," or basic logic circuits, believed to be the world's most complex ASIC to date. As with the previous ASIC technology, Cisco plans to work with IBM to develop new custom chips that take advantage of the reduced power consumption and increased performance this new process affords.
"With each progressive iteration of IBM's chip-building process, Cisco has been able to take advantage of the company's ability to deliver ever smaller, ever faster, higher functionality ASICs," said Tony Bates, vice president and general manager, IP POP Systems Group, Cisco Systems. "Integrating this type of leading edge technology into our high-end networking products helps us to deliver solutions based on evolving customer needs, including faster transport and protocol integration services as well as meeting the challenge of increasing performance while decreasing product size and footprints."
Cu-08 supports up to eight layers of copper wiring, separated by an advanced "low-k dielectric" insulation, linking hundreds of millions of transistors to form up to 72 million wireable gates -- all on a single chip. Cu-08 can be used to create complete system-on-a-chip designs, where elements such as processors, memory and analog functions all are combined on one piece of silicon.
Cu-08 also introduces several innovations to accelerate this integration of functions, including:
- "voltage islands," a design technique that can boost performance and reduce power consumption by allowing designers to alter the voltage within the chip to meet the needs of individual circuits;
- multiple library options of circuit designs, optimized for either performance or size, that customers can tap to build chips meeting their unique requirements;
- enhanced, compiled embedded DRAM memory capability allows designers to optimize the embedded DRAM performance, area and granularity to their specific application requirements; random data access time and random cycle times have been improved; hundreds of megabits of high performance on-chip memory can now be integrated with complex logic functions on a single ASIC.
Today, Cu-11 and SA-27E support mid-range mobile, home networking and gaming applications and Cu-08 will be extendable into these areas as well. All these ASIC design systems leverage IBM's production-proven Blue Logic methodology and are expected to strengthen IBM's position as a worldwide ASIC supplier. According to the latest figures from Gartner Dataquest, IBM was the number one worldwide ASIC vendor in 2001.
A design kit, allowing customers to begin developing chips based on Cu-08, is planned to be made available in the third quarter of this year.
|
Related News
- Denali's Industry-Standard PureSpec Verification IP Utilized by IBM for Latest CoreConnect Bus Architecture Toolkits for SoC designs
- Cycuity Sets New Standard for Semiconductor Chip Security Assurance with Next Generation of Radix Technology
- Arm Updates CSS Designs for Hyperscalers' Custom Chips
- Eliyan Sets New Standard for Chiplet Interconnect Performance with Latest PHY Delivering Data Rate of 64Gbps on 3nm Process Using Standard Packaging
- CV32E40P Core From OpenHW Group Sets the RISC-V Quality Standard For Open-Source Hardware IP
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |