Tabula Announces Availability of Stylus Compiler Version 2.8.2
Software release features new 100G reference designs
SANTA CLARA, Calif., February 13, 2014 – Tabula, Inc., announced today the availability of version 2.8.2 of its Stylus® compiler, supporting its ABAX®² P-Series of devices. Stylus 2.8.2 includes a new 3 × 40G-to-100G low-latency Ethernet bridge reference design, as well as a high-performance search engine soft IP core developed in collaboration with Algo-Logic Systems. These and the many other capabilities included in this release are designed to facilitate next-generation 100G networking equipment development and to further improve user experience.
The new capabilities and design kits introduced in the Stylus 2.8.2 release include:
- A 3 × 40G-to-100G Ethernet bridge: this reference design implements a fully functional 40G Ethernet to 100G Ethernet bridge providing transparent bidirectional bridging between the 40 GigE ports and the 100 GigE port and utilizing deficit-weighted round-robin (DWRR) traffic scheduler for aggregation of the 40 GigE ports. Features include:
- Three 40G Ethernet ports
- One 100G Ethernet port
- Forwarding table using Algo-Logic System’s EMSE2 soft IP core for 100 GigE traffic
- Support of multicast, broadcast and jumbo packets
- Host management interface serial port
- EMSE2 Hybrid soft IP core: created in collaboration with Algo-Logic Systems, this second generation exact-match search engine (EMSE2) delivers high-performance exact-match search capabilities. The EMSE2 Hybrid core performs up to 150 million searches per second (MSPS), sufficient for a 100G Ethernet traffic stream with minimum-sized 64-byte packets. If additional performance is needed, it is possible to use two or more replicated tables simultaneously. The core supports a wide range of key sizes, including up to 1.5 million entries, and very wide 640-bit keys for even the most demanding applications.
- DDR3 multi-port front-end reference (MPFE) design: the DDR3 MPFE allows up-to-eight independent (yet synchronous) hosts to drive a single DDR3 hard controller. The MPFE reference design has the following features:
- Enables up to eight independent ports (operating on the same clock) to drive a single hard DDR3 controller.
- Supports up to 2133 MT/s ×72 DDR3 throughput.
- Maintains a user interface that is consistent with the Tabula DDR3 subsystem, enabling easy integration into an existing design
- Uses deficit round-robin arbitration to cycle between valid ports to optimize DDR3 efficiency
More about Stylus compiler
Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula’s 3D Spacetime architecture; unleashing the ABAX2 3PLDs’ unmatched capabilities and achieving unparalleled performance with surprising ease. The software integrates cutting-edge timing-closure technologies, including sequential timing, router-aware placement, and automatic co-optimization of performance and density. In addition, to help users take full advantage of the ABAX2P1 device’s unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-port memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device’s on-chip RAM blocks.
Availability:
Stylus version 2.8.2 is available today.
About Tabula:
Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs) based on Tabula’s patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications, but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees, and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at www.tabula.com
|
Related News
- Tabula Announces Availability of Stylus Compiler Version 2.8.1
- Tabula Announces Availability of Stylus Compiler Version 2.7.1
- Tabula Announces Availability of Stylus Compiler Version 2.7
- Tabula Announces Availability of Stylus Compiler Version 2.6.2
- Tabula Releases Groundbreaking EDA Technologies in Support of its Suite of High-Performance Packet Processing Solutions
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |