Sonics-Denali Alliance Offers High Performance Memory System For Complex SOC Designs
Companies to Co-Market First Complete, OCP-Compliant Memory System Based on Databahn, SiliconBackplane MicroNetwork, and MemMax IP Cores
New Orleans, LA (39th DAC) - 2002/06/10 - Semiconductor intellectual property (SIP) providers Sonics, Inc. and Denali Software, Inc. today jointly announced a business and product partnership to co-market their respective intellectual property (IP) cores as a complete solution. The alliance creates the first open core protocol (OCP) -compliant memory system that integrates Denali's Databahn memory controller with Sonics' MemMax memory scheduler and SiliconBackplane MicroNetwork smart interconnect IP. The integrated products form a rapidly deployable and high performance solution to the problem of shared memory systems for complex multi-tasking system-on-chip (SOC) designs.
"Our close working relationship with Denali enables us to provide our mutual customers with a sophisticated solution to what has become a very thorny problem for SOC designers," said Grant Pierce, president and CEO of Sonics. "It makes sense for customers to obtain a completely integrated memory system solution from a coordinated point of contact. Using this commercial memory system, customers can bring more complex designs to market much faster than they could if they developed their own proprietary solutions."
The joint Sonics-Denali memory system is the only commercial solution that guarantees initiator cores both bandwidth and quality of service (QoS) to off-chip DRAM. Efficient utilization of memory bandwidth gives SOC designers the freedom to choose the most cost-effective DRAM for their particular applications. This highly configurable solution satisfies a wide range of memory system requirements and supports "plug and play" integration through compliance with the OCP interface standard. The pairing of Sonics' SMART IP and Denali's advanced memory controller cores provides configurability and support for multithreaded tasks, in addition to removing the routing congestion problems that typically occur with proprietary memory system approaches.
"We're alleviating a major headache on most SOC designers' list of concerns with this joint offering," said Sanjay Srivastava, president and CEO of Denali. "Customers have more than enough complexity to handle in their SOC designs. Integrating a very scalable, commercial memory system relieves a consistently difficult issue and allows customers to focus on their specific application value. Our joint solution provides the performance, flexibility, and reuse designers need to shorten their design cycles for the first as well as subsequent design projects."
Pricing and Availability
The joint Sonics-Denali OCP-compliant, memory system solution is available today from both companies. Please contact Sonics or Denali sales for pricing. The sales teams will provide total solution pricing for each design's optimal combination of products and support services.
Denali Software, Inc.
Denali Software Inc. is the world-leading provider of solutions for memory system selection, design, and implementation. Denali's eMemory.com is the most comprehensive and up-to-date source for memory component information, and houses an online infrastructure for its memory selection, memory controller cores, and memory simulation products. Denali also offers memory market research services, which provides customers with the most unbiased and forward-looking information on the technology and economics of semiconductor memories. More than 400 companies worldwide use Denali's tools, technology, and services to plan and develop memory systems for communications, consumer, and computer products. For more information, contact Denali at www.denali.com, or call (650) 461-7200.
About Sonics, Inc.
Sonics, Inc., the premier developer of MicroNetworks for "plug and play" integration of semiconductor intellectual property (IP) cores into system-on-chip (SOC) designs, is a privately held company in Mountain View, California. A Sonics MicroNetwork manages all communications between SOC subsystems, guarantees end-to-end performance, and ensures real-time quality of service. MicroNetwork technology enables flexible, platform-based SOC design through a robust development environment that uses an open standard core interface, the Open Core Protocol (OCP). Major semiconductor and systems companies have adopted Sonics' technology for SOC applications in the communications, networking and multimedia markets. For more information, see www.sonicsinc.com.
|
Related News
- Eureka Technology and Dolphin Technology offer complete DDR2/DDR3 Solution for High Performance SoC/ASIC Designs
- Oki Semiconductor offers a unique high performance, and fully qualified miniature W-CSP Package for low power SoC ASIC Designs
- sureCore designs special high performance multi-port memory for Semidynamics AI chip
- Open-Silicon to Demonstrate its High Bandwidth Memory (HBM2) IP Subsystem Solution for High Performance Computing and Networking Applications and Showcase its IoT Gateway SoC Reference Design for Smart City Applications at ARM TechCon 2017
- PLDA Announces XpressRICH4-AXI PCIe 4.0 IP, Providing a High Performance and Reliable AXI Bridge for SoC designs
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |