Jointwave zero-latency video transmission solution on Altera FPGA

March 26, 2014 -- Semiconductor IP H.264/H.265 silicon IP core provider Jointwave published a series of video encoding and decoding RTL IP cores. It has been successfully applied in business, industrial, avionics and military areas including UAV, remote medical treatments, wireless monitors WDE, video commanding, space crafts, etc.

The IP core’s highlights are listed below:

1. The encoder and decoder can achieve zero latency (less than 2 ms) while transmitting videos, which is why it is used in remote medications, wireless display, military combat commanding and drone controlling areas
2. Lossless video: A 1080P@60FPS HD video’s data size is 3Gbps. By implementing H.264 Intra Only mode with 4:4:4 color space, the video can achieve lossless quality at data size of only 50Mbps to 500Mbps. A 4Gbps fiber can transmit 8 to 20 streams of 1080P@60FPS simultaneously.
3. By using H.264 Intra Only compression does not require an external storage (i.e. DDR modules).
4. A single H.264 encoding IP core FPGA(Altera Stratix 10) with maximum performance can achieve 4K×4K@30fps super high resolutions.
5. Every H.264 encoding IP core FPGA(Altera Arria 10) Platform can achieve simultaneous 16 streams of 480P@30FPS encoding.
6. Color space supports 4：0：0 / 4：2：0 / 4：2：2 / 4：4：4
7. Color Depth supports 8bit /. 10bit / 12bit / 14bit
8. Compression ratio can range from 1/10～1/1000
9. Supports maximum bitrate of 500Mbps.
10. Anti-system-halting
11. Adaptive FPS according to signal channel changes

Jointwave Asia-Pacific chairman Thomas Wang says: “Jointwave’s H.264 IP core and the H.265 IP core order which will be delivered at the second half of 2014 has the maximum performance available on FPGA platforms (Altera Cyclone V & Arria V). It is the only system in the world that that can achieve zero-latency 1080P@60FPS on FPGA-based real-time codec system.”

zero-latency Demonstration photo on Arria V 1080P@60FPS

These H.264 IP cores have been applied onto ASIC in the form of RTL source code, and used by many FPGA customers in the form of RTL source code and netlist. Other than that Jointwave has build a high-end presentation and design reference platforms. This reference design works with 2 FPGA boards connected with Ethernet cable, or a board and a PC with Ethernet cable and UDP protocol. The encoder board receives uncompressed video data from HD media player via a HDMI cable, then encodes it to H.264 video stream, transmits the stream to the decoder board, the decoder board then decodes the stream to YUV data and displays it on another monitor. The demo system not only greatly reduces IP evaluation time for FPGA/ASIC design engineers, it also gives convenience to customers for prototype verifications.

About Altera:

Altera Corporation (NASDAQ: ALTR) is the leader in innovative custom logic solutions. It helps system and semiconductor companies to innovate, make products stand out and win the competition efficiently. Altera’s FPGA,SoC FPGA,CPLD and HardCopy®ASIC, combining with software tools, IP, integrated processors and customer support, provides 13,000 customers around the world with valuable programmable solutions.

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