Averant ups static functional verification
![]() |
Averant ups static functional verification
By Richard Goering, EE Times
October 16, 2001 (2:52 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011016S0082
SUNNYVALE, Calif. Averant Inc. has released Solidify version 2.5, which the company says expands its static functional verification tool. It adds a library of customizable automatic checks, advanced source-code debugging and hierarchical functional verification. A library of standard design checks generates thousands of Solidify properties to find the most common static errors. Checks look for stuck-at faults, deadlocked states and values, floating bus and bus contention, set-reset problems, dead code and other unwanted conditions. Interactive source-code debugging links specific HDL statements to the conditions that cause a property to fail. Averant's Solidify produces values for the significant variables and clock cycles spanned by the failing property. The new version is available now on Windows, Linux and Solaris platforms with a list price of $40,000.
Related News
- Averant ups static functional verification
- IAR unveils Functional Safety version of IAR Embedded Workbench for Arm equipped with certified static analysis capabilities
- Dolphin Design Selects Imperas for Processor Functional Design Verification
- Imperas releases new updates, test suites, and functional coverage library to support the rapid growth in RISC-V Verification
- Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library
Breaking News
- Siemens delivers certified and automated design flows for TSMC 3DFabric technologies
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |