Common Platform in Preparation for SOI, FinFETs at 10nm
Peter Clarke, Electronics360
08 April 2014
A team of engineers from IBM Microelectronics, Globalfoundries, Samsung, STMicroelectronics and UMC are due to present a 10nm logic platform that supports FinFETs on both bulk CMOS and on silicon-on-insulator wafers.
The presentation of paper 2.2 is set to be one of the highlights of the Symposium on VLSI Technology due to take place June 9 to 12 at Honolulu, Hawaii. It represents a coming together of the interests of the FinFET and fully-depleted silicon-on-insulator (FDSOI) camps, but not yet a complete merging.
E-mail This Article | Printer-Friendly Page |
Related News
- Silvaco Expands its Victory TCAD and Digital Twin Modeling Platform to Planar CMOS, FinFET and Advanced CMOS Technologies
- GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform
- SEMIFIVE Achieves Mass Production Milestone of its SoC Platform
- Faraday Launches Cortex-A53-based Platform to Accelerate FinFET SoC Development
- Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform
Breaking News
- Micon Global and Silvaco Announce New Partnership
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition