Krivi announces 28nm silicon proven DDR3/3L PHY with ARM CoreLink Technology

BANGALORE, India -- April 23, 2014 —Krivi Semiconductor (www.krivisemi.com) has announced its initial working silicon of a 28nm DDR3 PHY. The new Krivi DDR3/3L PHY with ARM® CoreLink™ DMC-400 Dynamic Memory Controller is JEDEC compatible, feature rich and supports maximum speeds of up to 2.133Gbps. Synthesizable and PnR friendly, this latest RTL from Krivi supports custom floor-planning to suit modern SoC providers who require faster-time-to-market or more stringent overall PHY area requirements. Numerous patent-pending, jitter tolerant training algorithms and superior analog components will enable Krivi SoC partners to use DDR without using an oscilloscope during chip bring-up.

“Krivi’s state of the art DDR PHY adopts a SoC-friendly integration and implementation architecture. This, combined with its detailed real-world pre-silicon verification, ensures easy integration, less iterations and quick chip bring-up, leading to predictable customer success,” said Nidhir Kumar, Krivi CEO and co-founder.

Krivi offers advanced training to correctly align READ and WRITE data bits at the center of data strobe without any side band signaling. Its innovative automatic write-leveling caters to all types of DIMMs. Dynamic gate training maintains on-track capture of read data strobe without consuming any system bandwidth. All the training could be independently performed on each of the available chip selects.

Krivi PHY corrects up to a one-quarter clock cycle of skew in each of the READ and WRITE data bits. This virtually alleviates the necessity of tightly matched PCB routing requirements and recovers timing margin from DRAM READ/WRITE budgets.

Krivi’s DDR PHY requires very little register programming but offers extensive registers for power and performance fine tuning. Every DLL and training value is observable and could be bypassed if required. To minimize power integrity challenges, PHY incorporates mechanisms for in-rush current control during OTF data width selection and low power entry/wakeup. The Krivi PHY offers advanced low power modes and automatic re-calibration post wakeup. IO retention allows shutdown of PHY supplies with the exception of a small live IO domain to keep DRAM in self-refresh for data coherency.

The PHY offers loop back BIST for all the analog intensive paths including READ, WRITE and ADD/CMD clubbed with its comprehensive DFT solution.

The PHY uses a DFI interface and provides programmable options to hook to virtually any memory controller. Krivi PHY is extensively verified for the ARM ecosystem including ARM memory controllers.

Availability:

X72 and X32 DDR3/3L silicon-proven hard IP are available for immediate license. Krivi currently offers technology migration services at every leading technology node, including TSMC’s 28HPM technology which the DDR3 PHY IP was developed in.

Partner Quote:

“As design cycles of semiconductor companies continue to shorten, those firms look to source proven building blocks as part of their solution,” said Vincent Korstanje, vice president of marketing, systems and software group, ARM. “Demonstrating the combination of the Krivi DDR3 PHY with the ARM CoreLink DMC-400 in silicon is a major step towards delivering that confidence level to our mutual customers.”

About Krivi:

Krivi Semiconductor is an IP company with specialization in DDR PHY, IO pad libraries and Analog macros. Highly motivated engineering team at Krivi takes advantage of decades of successful mass volume IP creation experience to bring best-in-class AMS and wired interconnect PHY IP products. Our flexible business model combined with world class engineering team adds tremendous value to the customers in building their SoC within time and budget. For more information about Krivi visit www.krivisemi.com.