Altera Raises the Bar for IP Core Quality
I-Tested is the Industry's First Intellectual Property Certification Program for Interoperability with Other Hardware
San Jose, Calif., June 25, 2002 -- Altera Corporation (NASDAQ: ALTR) today announced its I-Tested (interoperability-tested) certification program, the industry's first intellectual property (IP) certification program to ensure successful interoperability between IP implemented in FPGAs and other hardware. Through the I-Tested certification program, IP cores implementing complex protocols are tested in an Altera FPGA on an evaluation board. This test process certifies interoperability with other hardware, such as industry-standard ASSPs, to give Altera customers unparalleled confidence in designing hardware systems.
"Customers view hardware verification of interface IP cores such as PCI and POS-PHY as absolutely critical, but this is a time-consuming and expensive task," said Justin Cowling, director of marketing for the intellectual property business unit at Altera. "The I-Tested certification of our MegaCore® and AMPPSM (Altera Megafunction Partner Program) partners' IP ensures that we have done this verification and are passing the savings on to our customers with quality, tested IP."
In addition to the rigorous software simulation that is applied to all IP cores offered by Altera, each I-Tested core is tested in hardware to verify interoperability with industry-standard devices on both the protocol and I/O timing levels. I-Tested certified cores are accompanied by detailed documentation about the hardware platform, key components used, and test descriptions and results.
"Through the VCX TradeFloor, we have seen tremendous demand from customers for proof that IP will actually work with other devices in their system," said Andy Travers, CEO at Virtual Component Exchange (VCX), the first regulated exchange for trading semiconductor IP (SIP) or virtual components (VCs). "Certification programs, such as Altera's I-Tested program, will meet this demand, saving customers time and money when implementing their IP in hardware."
Availability
The following I-Tested certified cores are available now. For up-to-date availability of I-Tested certified IP cores please visit the IP MegaStore™ web site at http://www.altera.com/IPmegastore.
Core | Vendor |
PCI Compiler (32/64-bit, 33/66 MHz, Master/Target) | Altera Corporation |
10/100 Ethernet MAC | Altera Corporation |
DDR SDRAM Controller | Altera Corporation |
PPP Packet Processors, 155/622 Mbps | Altera Corporation |
T3 Framer | Altera Corporation |
USB Function Controller | Cast, Inc. |
ATM Receive Processor | Innocor Ltd. |
Packet Over SONET Controller | Innocor Ltd. |
AAL5 Segmentation and Reassembly | Innocor Ltd. |
32/64-Bit PCI Bus Master/Target Interface | PLDApplications |
Nios-to-PCI Bridge | PLDApplications |
AMBA-AHB-PCI Bridge | PLDApplications |
About the Altera Megafunction Partners Program (AMPP)
The Altera Megafunction Partners Program, established in August 1995, was created to bring the advantages of design reuse to users of Altera PLDs. AMPP is an alliance between Altera and developers of IP cores that encourages megafunction development. Altera provides technical information and training to the AMPP partners, who create and support IP cores targeted for Altera PLDs. Currently, there are over 30 AMPP partners who offer more than 150 megafunctions. Customers may request a free evaluation of any of these cores through Altera's megafunction listings at http://www.altera.com/IPmegastore.
About Altera
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at http://www.altera.com.
|
Intel FPGA Hot IP
Related News
- SiFive Raises RISC-V performance bar with New Best-in-Class SiFive Performance P650 Processor
- Gyrfalcon's New Chip Raises Bar (12.6 TOPS/W) on High Performance Edge AI with Lower Power Use
- Ultra-low power 'Whisper' architecture raises the bar for connectivity IP in IoT, wearables and more
- Huawei Names Altera 2012 Excellent Core Partner for Delivering Quality, Leading-edge Products and Superior Technical Support
- Microtronix Enhances 1080p Display Quality With Altera Cyclone III FPGA-Based Development Kit
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |