MOSCAD Design & Automation Releases Ultra low-power Voltage regulator cell in 55nm
June 25, 2014 -- MOSCAD Design & Automation has released a new version of its ultra-low power voltage regulator cell in UMC 55nm Low Power CMOS process.
Total power consumption, to which leakage is an increasing contributor, is increasing as technology scaling progresses. This poses a challenge in reducing power consumption of cells designed to be used in 65/55 nm and below.
The VR3_12_1 provides a 1.2V output with an input ranging from 1.6 to 3.6 V. It offers ultra-low quiescent current of less than 2µA, including the built-in Bandgap reference circuit. This makes the cell ideally suited for wireless portable devices and any other battery operated devices.
The VR3_12_1 is a member of MOSCAD’s family of High-Performance analog and mixed-signal IP which can be easily integrated into Analog- or Mixed-Signal SoC’s.
Specifications and product brief
|
MOSCAD Design & Automation Hot IP
Related News
- SESAME BIV standard cell library: Dolphin Integration's ultra low-power solution for always-on blocks
- Aplus to Provide Low-Power, Low Voltage (1.8V) Operation EEPROM Macro Solution at UMC
- Massana, XEMICS Partner To Offer A Combined RISC and DSP Core For Ultra Low-Power, Low-Voltage Applications
- LeapMind's Ultra Low-Power AI accelerator IP "Efficiera" Achieved industry-leading power efficiency of 107.8 TOPS/W
- eMemory and UMC Expand Low-Power Memory Solutions for AIoT and Mobile Markets with 22nm RRAM Qualification
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |