English
Synopsys snaps up Mentor IP guru
 |
Synopsys snaps up Mentor IP guru
By Peter Clarke, Semiconductor Business News
July 4, 2002 (5:40 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020703S0019
SOPHIA ANTIPOLIS, France - Pierre Bricaud, formerly vice president of SOC strategic relationships for Mentor Graphics and an important part of the Wilsonville, Ore.-based company's circuit intellectual property (IP) strategy, has been recruited by Synopsys Inc., Mentor's main EDA rival. Bricaud has moved to take a European role within the R&D organization of Mountain View, Calif.-based Synopsys, working with system-on-chip and IP design teams within European customers to help them acquire suitable tools and IP blocks. Bricaud reports to Mike Keating with whom he co- authored the Reuse Methodology Manual in 1998. Although Bricaud and Keating are and were engineering managers working in the commercial environment rather than academics this is held to be a useful text book on the design of circuit blocks for re-use -- and a part of attempts by EDA companies to help design engineers to work at higher levels of abstraction.
Related News
- Synopsys and Siemens Team Up to Expand and Extend Electronic Design Automation Collaboration
- Synopsys, Mentor spiff up design-for-test tools
- Synopsys Approves Stock Repurchase Program with Authorization Up to $1.5 Billion
- Synopsys Approves Stock Repurchase Program with Authorization Up to $1 Billion
- Synopsys Replenishes Repurchase Authorization up to $500 Million
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
|
E-mail This Article | 
|
|
Printer-Friendly Page |