English
IP And FinFETs At Advanced Nodes - Part 2
Ed Sperling, Semiconductor Engineering
July 21, 2014
Experts at the table, part 2: FinFETs become more complex at each new node; stacked die IP challenges; including the package in the simulation; local versus global design concerns.
Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation.
Related News
- MIPI CSI 3, DSI 2 Tx & Rx Advanced Controller & PHY IP Cores available in major Fabs & Nodes for SOC Designs for Imaging and Display Applications
- SMIC: Advanced Process Technologies and Gov't Funding (Part 2)
- IP And FinFETs At Advanced Nodes
- eMemory Won TSMC OIP Partner of the Year Award for the Outstanding Development of its NVM IP on Advanced Nodes
- Faraday Adds Video Interface IP to Support All Advanced Planar Nodes on UMC Platform
Breaking News
- SIA Statement on Biden Administration Action Imposing New Export Controls on AI Chips
- BrainChip Brings Neuromorphic Capabilities to M.2 Form Factor
- Exostiv Labs Unveils AMD Versal Adaptive SoC Device Support for Exostiv and Exostiv Blade Platforms
- TSMC December 2024 Revenue Report
- NASA Awards Alphacore Four Contracts for Radiation Hardened Microelectronics Innovation
Most Popular
- Eighteen New Semiconductor Fabs to Start Construction in 2025, SEMI Reports
- VeriSilicon's Display Processing IP DC8200-FS has achieved ISO 26262 ASIL B certification
- OPENEDGES and TAKUMI partner to promote ORBIT Memory Subsystem IP in Japan
- CEVA Opens New Research and Development Center in Bristol, U.K.
- TTTech divests strategic stake in landmark transaction to NXP to fuel future growth with technology investments in core business
|
E-mail This Article | 
|
|
Printer-Friendly Page |